PATH DELAY DESIGN-FOR-TESTABILITY USING SNOOPING FOR FUNCTIONAL REGISTER-TRANSFER LEVEL CIRCUITS
Testing of VLSI circuits is important to ensure the reliability of digital systems. Due to the advancement in process technology, more performance defects occur. Path delay testing ensures the timing accuracy and functional correctness of the VLSI circuits and has become crucial. The standard sca...
Saved in:
| 主要作者: | |
|---|---|
| 格式: | Thesis |
| 語言: | English |
| 出版: |
2017
|
| 主題: | |
| 在線閱讀: | http://utpedia.utp.edu.my/22054/1/PATH%20DELAY%20DESIGN-FOR-TESTABILITY%20USING%20SNOOPING%20FOR%20FUNCTIONAL%20REGISTER-TRANSFER%20LEVEL%20CIRCUITS%20%28Ateeq-ur-Rehman%20Shaheen_G01838%29.pdf http://utpedia.utp.edu.my/22054/ |
| 標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|