SHAHEEN, A. (2017). PATH DELAY DESIGN-FOR-TESTABILITY USING SNOOPING FOR FUNCTIONAL REGISTER-TRANSFER LEVEL CIRCUITS.
Chicago Style CitationSHAHEEN, ATEEQ-UR-REHMAN. PATH DELAY DESIGN-FOR-TESTABILITY USING SNOOPING FOR FUNCTIONAL REGISTER-TRANSFER LEVEL CIRCUITS. 2017.
MLA CitationSHAHEEN, ATEEQ-UR-REHMAN. PATH DELAY DESIGN-FOR-TESTABILITY USING SNOOPING FOR FUNCTIONAL REGISTER-TRANSFER LEVEL CIRCUITS. 2017.
Warning: These citations may not always be 100% accurate.