Verification of Microprocessor without Interlocked Pipeline (MIPS) Processor using Self-Checking Testbench
MIPS stand for Microprocessor without Interlocked Pipeline Stages. It is a reduced instruction set computer (RISC) instruction set architecture (ISA). RISC is a wellstablished architecture due to its efficiency and simplicity. Thus, it is widely used in the processor industry. However, verifying and...
محفوظ في:
| المؤلف الرئيسي: | |
|---|---|
| التنسيق: | Final Year Project / Dissertation / Thesis |
| منشور في: |
2023
|
| الموضوعات: | |
| الوصول للمادة أونلاين: | http://eprints.utar.edu.my/5957/1/Teng_Wen_Jun_21AGM06710.pdf http://eprints.utar.edu.my/5957/ |
| الوسوم: |
إضافة وسم
لا توجد وسوم, كن أول من يضع وسما على هذه التسجيلة!
|