Verification of Microprocessor without Interlocked Pipeline (MIPS) Processor using Self-Checking Testbench
MIPS stand for Microprocessor without Interlocked Pipeline Stages. It is a reduced instruction set computer (RISC) instruction set architecture (ISA). RISC is a wellstablished architecture due to its efficiency and simplicity. Thus, it is widely used in the processor industry. However, verifying and...
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| フォーマット: | Final Year Project / Dissertation / Thesis |
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2023
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| オンライン･アクセス: | http://eprints.utar.edu.my/5957/1/Teng_Wen_Jun_21AGM06710.pdf http://eprints.utar.edu.my/5957/ |
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| 要約: | MIPS stand for Microprocessor without Interlocked Pipeline Stages. It is a reduced instruction set computer (RISC) instruction set architecture (ISA). RISC is a wellstablished architecture due to its efficiency and simplicity. Thus, it is widely used in the processor industry. However, verifying and validating the correctness of the processor if a complex work as it consists of about 111 total instructions (Stanford.edu, 2020). Various types of hazards might be arise due to the complexity of the pipeline structures. Thus, the verification process will be time consuming as validators need to verify the whole design by checking the waveforms after they make some minor changes. This project is to improve the efficiency of verification process of the current RISC32 5-stage pipeline processor that developed in Universiti Tunku Abdul Rahman which is under Faculty of Information Technology by developing a complete self-checking testbench using SystemVerilog to verify the functional correctness of the MIPS design at system level. |
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