Design and Implementation of the Quadrature Voltage Controlled Oscillator for Wireless Receiver Applications Utilizing 0.13 {Lm and 0.18 {Lm Deep Sub-Micron RF CMOS Technology
The field of high-frequency circuit design is receiving significant industrial attention due to variety of radio frequency and microwave applications. This work proposes the low power, low phase noise and low phase error quadrature voltage controlled oscillator (LP3 - QVCO) for wireless receiver...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2009
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| Subjects: | |
| Online Access: | http://utpedia.utp.edu.my/id/eprint/8019/1/2009%20PhD%20-%20Design%20and%20Implementatin%20of%20The%20Quadrature%20Voltage%20Controled%20Oscillator%20For%20Wireless%20R.pdf http://utpedia.utp.edu.my/id/eprint/8019/ |
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| Summary: | The field of high-frequency circuit design is receiving significant industrial attention
due to variety of radio frequency and microwave applications. This
work proposes the low power, low phase noise and low phase error quadrature
voltage controlled oscillator (LP3 - QVCO) for wireless receiver applications.
An enhanced investigation and design of the low power, low phase noise and
low phase error quadrature voltage controlled oscillator (LP3 - QVCO) is
carried out in comparison to conventional LC- QVCO. The design, implementation
and characterization of the complementary LP3
- QVCO is carried
out with the integration of 40 S1 source damping resistor (Rdmp), tail biasing
resistor (Rtait) and multifinger gate width configuration of the pMOS varactors
and 50 S1 impedance of common drain output buffers. The LP3 - QV CO
implementation is carried out using 0.18 p,m, 6 metal, 1 poly, 1.8 V and 0.13
p,m, 8 metal, 1 poly, 1.2 V deep sub-micron CMOS and RF CMOS process
technologies. The three different designs with the center frequencies of 2.8
GHz, 3.1 GHz and 3.8 GHz are implemented using 0.18 p,m CMOS and RF
CMOS process technology. The remaining four designs with the center frequencies
of 4.35 GHz and 5 GHz are implemented using 0.13 p,m RF CMOS
process technologies. The LP3 - QVCO design exhibit the measured phase
noise of -110.13 dBc/Hz and -108.54 dBc/Hz at the offset frequency of 1 MHz,
with multifinger gate width configuration of pMOS varactor (3.125 p,m x 64
= 200 p,m) and (8 p,m x 25 = 200 p,m), respectively. The phase noise im
provement of 1.63 dB is achieved in LP3 - QVCO design implemented with
(3.125 I'm x 64 = 200 I'm) mult.ifinger gate width configuration of pMOS
varactor in comparison to (8 f.tm x 25 = 200 f.tm). The measured center frequency
of the LP3 - QVCO is 4.35 GHz with the frequency tuning range of
4.21 GHz to 4.44 GHz. Both LP3 - QVCO core power dissipation is 3.36
m W from 1.2 V de power supply. The measured phase error is less than 0.2'.
The calculated figure of merit (FOM) is -177.6 dBc/Hz. The symmetrical
spiral inductor is also used with patterned ground shield (PGS). The quality
(Q) factor of inductor is 18.6 and is implemented using 0.13 f.tm RF CMOS
process technology. |
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