Design Methodology to Achieve Good Testability of VLSI Chips: An Industrial Perspective
Many of today’s Very Large Scale Integration (VLSI) chips are digital design that has hundreds of thousands to millions of transistors per chip. Testing of such large VLSI chips proves to be a challenge. One method of addressing this challenge is the introduction of Design For Test (DFT) featur...
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| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Published: |
2009
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| Subjects: | |
| Online Access: | http://eprints.utp.edu.my/5340/1/stamp.jsp%3Ftp%3D%26arnumber%3D4786782%26tag%3D1 http://eprints.utp.edu.my/5340/ |
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