System-on-chip (SoC) testing using adhoc high-level design for-testability method
The design of System-on-Chip (SoC) is becoming more complex and number of transistors in a chip has increased from millions of gates to billions of gates nowadays but the number of Input/Output pins still remains about the same. In this case, design-for-test (DFT) becomes so important in order to ma...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2009
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| Online Access: | http://eprints.utm.my/id/eprint/18577/1/ChengChenKongMFKE2009.pdf http://eprints.utm.my/id/eprint/18577/ |
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