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Delay Fault Modelling/Simulation using VHDL-AMS in Multi Vdd Systems

With the growing density of Very Large Scale Integrated(VLSI circuits, traditional digital fault simulation is no longer a viable option. This is because of analogue-like behaviour in digital circuits. The need for fast fault simulation is one of the main requirements in test pattern generation. The...

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Main Authors: Zain Ali, Noohul Basheer, Mark, Zwolinski, Ahmadi, Arash
Format: Conference or Workshop Item
Published: 2008
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utp.edu.my/4806/1/Delay_Fault_ModellingSimulationusingVHDL-AMSinMulti-VddSystems.pdf
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4559309
http://eprints.utp.edu.my/4806/
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spelling my.utp.eprints.48062017-01-19T08:26:15Z Delay Fault Modelling/Simulation using VHDL-AMS in Multi Vdd Systems Zain Ali, Noohul Basheer Mark, Zwolinski Ahmadi, Arash TK Electrical engineering. Electronics Nuclear engineering With the growing density of Very Large Scale Integrated(VLSI circuits, traditional digital fault simulation is no longer a viable option. This is because of analogue-like behaviour in digital circuits. The need for fast fault simulation is one of the main requirements in test pattern generation. The trade off between accurate simulations at transistor level, as in SPICE and fast simulationat gate level using a Hardware Descriptive Language(HDL)can be achieved by using behavioural modelling languages such as VHDL-AMS. In this paper, we have demonstrated that behavioural fault simulation for resistive faults can produce fast and accurate results. 2008-05-11 Conference or Workshop Item PeerReviewed application/pdf http://eprints.utp.edu.my/4806/1/Delay_Fault_ModellingSimulationusingVHDL-AMSinMulti-VddSystems.pdf http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4559309 Zain Ali, Noohul Basheer and Mark, Zwolinski and Ahmadi, Arash (2008) Delay Fault Modelling/Simulation using VHDL-AMS in Multi Vdd Systems. In: PROC. 26th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2008), 11-14 May, 2008, Nis, Serbia. http://eprints.utp.edu.my/4806/
institution Universiti Teknologi Petronas
building UTP Resource Centre
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Petronas
content_source UTP Institutional Repository
url_provider http://eprints.utp.edu.my/
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Zain Ali, Noohul Basheer
Mark, Zwolinski
Ahmadi, Arash
Delay Fault Modelling/Simulation using VHDL-AMS in Multi Vdd Systems
description With the growing density of Very Large Scale Integrated(VLSI circuits, traditional digital fault simulation is no longer a viable option. This is because of analogue-like behaviour in digital circuits. The need for fast fault simulation is one of the main requirements in test pattern generation. The trade off between accurate simulations at transistor level, as in SPICE and fast simulationat gate level using a Hardware Descriptive Language(HDL)can be achieved by using behavioural modelling languages such as VHDL-AMS. In this paper, we have demonstrated that behavioural fault simulation for resistive faults can produce fast and accurate results.
format Conference or Workshop Item
author Zain Ali, Noohul Basheer
Mark, Zwolinski
Ahmadi, Arash
author_facet Zain Ali, Noohul Basheer
Mark, Zwolinski
Ahmadi, Arash
author_sort Zain Ali, Noohul Basheer
title Delay Fault Modelling/Simulation using VHDL-AMS in Multi Vdd Systems
title_short Delay Fault Modelling/Simulation using VHDL-AMS in Multi Vdd Systems
title_full Delay Fault Modelling/Simulation using VHDL-AMS in Multi Vdd Systems
title_fullStr Delay Fault Modelling/Simulation using VHDL-AMS in Multi Vdd Systems
title_full_unstemmed Delay Fault Modelling/Simulation using VHDL-AMS in Multi Vdd Systems
title_sort delay fault modelling/simulation using vhdl-ams in multi vdd systems
publishDate 2008
url http://eprints.utp.edu.my/4806/1/Delay_Fault_ModellingSimulationusingVHDL-AMSinMulti-VddSystems.pdf
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4559309
http://eprints.utp.edu.my/4806/
_version_ 1738655371172511744
score 13.211869

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