Delay Fault Modelling/Simulation using VHDL-AMS in Multi Vdd Systems
With the growing density of Very Large Scale Integrated(VLSI circuits, traditional digital fault simulation is no longer a viable option. This is because of analogue-like behaviour in digital circuits. The need for fast fault simulation is one of the main requirements in test pattern generation. The...
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| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Published: |
2008
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| Subjects: | |
| Online Access: | http://eprints.utp.edu.my/4806/1/Delay_Fault_ModellingSimulationusingVHDL-AMSinMulti-VddSystems.pdf http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4559309 http://eprints.utp.edu.my/4806/ |
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| Summary: | With the growing density of Very Large Scale Integrated(VLSI circuits, traditional digital fault simulation is no longer a viable option. This is because of analogue-like behaviour in digital circuits. The need for fast fault simulation is one of the main requirements in test pattern generation. The trade off between accurate simulations at transistor level, as in SPICE and fast simulationat gate level using a Hardware Descriptive Language(HDL)can be achieved by using behavioural modelling languages such as VHDL-AMS. In this paper, we have demonstrated that behavioural fault simulation for resistive faults can produce fast and accurate results. |
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