Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed methodology handles both flat bus single processor SOC and hierarchical bus multiprocessor SOC. It is based on a resource graph manipula...
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| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Published: |
2007
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| Subjects: | |
| Online Access: | http://eprints.utp.edu.my/3590/1/fawnizu_aspdac2008.pdf http://eprints.utp.edu.my/3590/ |
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