Cover Image

Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses

An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed methodology handles both flat bus single processor SOC and hierarchical bus multiprocessor SOC. It is based on a resource graph manipula...

Full description

Saved in:
Bibliographic Details
Main Authors: Hussin, Fawnizu Azmadi, Yoneda, Tomokazu, Orailoglu, Alex, Fujiwara, Hideo
Format: Conference or Workshop Item
Published: 2007
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utp.edu.my/3590/1/fawnizu_aspdac2008.pdf
http://eprints.utp.edu.my/3590/
Tags: Add Tag
No Tags, Be the first to tag this record!
id my.utp.eprints.3590
record_format eprints
spelling my.utp.eprints.35902017-01-19T08:26:58Z Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses Hussin, Fawnizu Azmadi Yoneda, Tomokazu Orailoglu, Alex Fujiwara, Hideo TK Electrical engineering. Electronics Nuclear engineering An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed methodology handles both flat bus single processor SOC and hierarchical bus multiprocessor SOC. It is based on a resource graph manipulation and a packet-based packet set scheduling methodology. The resource graph is decomposed into a set of test configuration graphs, which are then used to determine the optimum test configurations and test delivery schedule under a given power constraint. In order to validate the effectiveness of the proposed methodology, a number of experiments are run on several modified benchmark circuits. The results clearly underscore the advantages of the proposed methodology. 2007-01 Conference or Workshop Item PeerReviewed application/pdf http://eprints.utp.edu.my/3590/1/fawnizu_aspdac2008.pdf Hussin, Fawnizu Azmadi and Yoneda, Tomokazu and Orailoglu, Alex and Fujiwara, Hideo (2007) Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. In: 12th Asia and South Pacific Design Automation Conference (ASP-DAC'07), Jan. 23-26 2007 , Yokohama, Japan. http://eprints.utp.edu.my/3590/
institution Universiti Teknologi Petronas
building UTP Resource Centre
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Petronas
content_source UTP Institutional Repository
url_provider http://eprints.utp.edu.my/
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Hussin, Fawnizu Azmadi
Yoneda, Tomokazu
Orailoglu, Alex
Fujiwara, Hideo
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
description An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed methodology handles both flat bus single processor SOC and hierarchical bus multiprocessor SOC. It is based on a resource graph manipulation and a packet-based packet set scheduling methodology. The resource graph is decomposed into a set of test configuration graphs, which are then used to determine the optimum test configurations and test delivery schedule under a given power constraint. In order to validate the effectiveness of the proposed methodology, a number of experiments are run on several modified benchmark circuits. The results clearly underscore the advantages of the proposed methodology.
format Conference or Workshop Item
author Hussin, Fawnizu Azmadi
Yoneda, Tomokazu
Orailoglu, Alex
Fujiwara, Hideo
author_facet Hussin, Fawnizu Azmadi
Yoneda, Tomokazu
Orailoglu, Alex
Fujiwara, Hideo
author_sort Hussin, Fawnizu Azmadi
title Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
title_short Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
title_full Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
title_fullStr Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
title_full_unstemmed Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
title_sort core-based testing of multiprocessor system-on-chips utilizing hierarchical functional buses
publishDate 2007
url http://eprints.utp.edu.my/3590/1/fawnizu_aspdac2008.pdf
http://eprints.utp.edu.my/3590/
_version_ 1738655274858708992
score 13.211869

Similar Items