New asymmetrical modular multilevel inverter topology with reduced number of switches
In this article, a new single-phase multilevel inverter is introduced with a reduced number of power switches and reduced voltage stress on power switches. The proposed topology consists of four input dc sources and nine semiconductor switches (eight unidirectional and one bidirectional switch). The...
保存先:
| 主要な著者: | , , , , , |
|---|---|
| フォーマット: | 論文 |
| 言語: | English |
| 出版事項: |
Institute of Electrical and Electronics Engineers Inc.
2021
|
| 主題: | |
| オンライン･アクセス: | http://eprints.utm.my/id/eprint/94439/1/ShahrinMdAyob2021_NewAsymmetricalModularMultilevelInverterTopology.pdf http://eprints.utm.my/id/eprint/94439/ http://dx.doi.org/10.1109/ACCESS.2021.3057554 |
| タグ: |
タグ追加
タグなし, このレコードへの初めてのタグを付けませんか!
|
| 要約: | In this article, a new single-phase multilevel inverter is introduced with a reduced number of power switches and reduced voltage stress on power switches. The proposed topology consists of four input dc sources and nine semiconductor switches (eight unidirectional and one bidirectional switch). The topology can be used for asymmetrical voltage source configuration to generate seventeen voltage levels. The extended topology is constructed by a series connection of the topology circuit to produce higher voltage levels with less voltage stress on the switches without modifying the existing structure. Comparison is made with traditional and recently introduced topologies based on the number of power switches, dc sources, total blocking voltage of switches, and gate driver circuits, to prove the proposed topology's superiority. A simple nearest level modulation has been deployed as the switching scheme. Validation on the viability of the proposed topology has been carried out through simulation and hardware experimental setup. |
|---|