Staff View: A 88 μW digital phase-domain GFSK demodulator compatible with low-if and zero-IF receiver with preamble detection for BLE

A 88 μW digital phase-domain GFSK demodulator compatible with low-if and zero-IF receiver with preamble detection for BLE

Unlike conventional analog-to-digital converter (ADC), phase-domain ADC (Ph-ADC) is more power efficient for the implementation of fully digital Gaussian frequency shift keying (GFSK) demodulator in bluetooth low energy (BLE). Besides, Ph-ADC based demodulator is flexible to pair with low-IF and zer...

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Main Authors:	Ung, Shen Jie, Ab. Rahman, Ab. Al-Hadi
Format:	Article
Language:	English
Published:	Turkiye Klinikleri 2020
Subjects:	TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/93457/1/UngShenJie2020_A88uWDigitalPhaseDomain.pdf http://eprints.utm.my/id/eprint/93457/ http://dx.doi.org/10.3906/ELK-1912-155
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spelling	my.utm.934572021-11-30T08:33:30Z http://eprints.utm.my/id/eprint/93457/ A 88 μW digital phase-domain GFSK demodulator compatible with low-if and zero-IF receiver with preamble detection for BLE Ung, Shen Jie Ab. Rahman, Ab. Al-Hadi TK Electrical engineering. Electronics Nuclear engineering Unlike conventional analog-to-digital converter (ADC), phase-domain ADC (Ph-ADC) is more power efficient for the implementation of fully digital Gaussian frequency shift keying (GFSK) demodulator in bluetooth low energy (BLE). Besides, Ph-ADC based demodulator is flexible to pair with low-IF and zero-IF receiver, opposed to limiter based demodulator that work with low-IF receiver only. Yet, currently reported Ph-ADC based demodulator lack of preamble detection for BLE which will be used as symbol clock synchronization. In this work, a Ph-ADC based demodulator is proposed with the feature of preamble detection on BLE's packet. The detected preamble is used for symbol clock recovery and compensation of carrier frequency offset in a BLE packet. Besides, the proposed demodulator is flexible to demodulate IF or baseband signal by simply configuring a parameter value. Using MATLAB, minimum signal-to-noise Ratio (SNR) needed to demodulate BLE packet is estimated using Monte Carlo simulation with 99% confidence level. For hardware implementation, the proposed demodulator is implemented at RTL in Synopsys and its layout is generated using 0.18 μm CMOS technology. To understand the trade-off between power consumption, layout size and minimum SNR needed, the proposed Ph-ADC based demodulator is scaled to a different combination of 4-bit to 6-bit resolution and 2 MHz to 16 MHz sampling rate. Configuration with the best trade-off for the proposed Ph-ADC demodulator can achieve bit error rate (BER) of 0.1% at SNR of 12.5 dB and able to tolerate carrier frequency offset of ± 200 kHz while using only half the power needed by state of the art limiter based demodulator. Turkiye Klinikleri 2020-07 Article PeerReviewed application/pdf en http://eprints.utm.my/id/eprint/93457/1/UngShenJie2020_A88uWDigitalPhaseDomain.pdf Ung, Shen Jie and Ab. Rahman, Ab. Al-Hadi (2020) A 88 μW digital phase-domain GFSK demodulator compatible with low-if and zero-IF receiver with preamble detection for BLE. Turkish Journal of Electrical Engineering and Computer Sciences, 28 (4). pp. 2183-2199. ISSN 1300-0632 http://dx.doi.org/10.3906/ELK-1912-155 DOI:10.3906/ELK-1912-155
institution	Universiti Teknologi Malaysia
building	UTM Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Teknologi Malaysia
content_source	UTM Institutional Repository
url_provider	http://eprints.utm.my/
language	English
topic	TK Electrical engineering. Electronics Nuclear engineering
spellingShingle	TK Electrical engineering. Electronics Nuclear engineering Ung, Shen Jie Ab. Rahman, Ab. Al-Hadi A 88 μW digital phase-domain GFSK demodulator compatible with low-if and zero-IF receiver with preamble detection for BLE
description	Unlike conventional analog-to-digital converter (ADC), phase-domain ADC (Ph-ADC) is more power efficient for the implementation of fully digital Gaussian frequency shift keying (GFSK) demodulator in bluetooth low energy (BLE). Besides, Ph-ADC based demodulator is flexible to pair with low-IF and zero-IF receiver, opposed to limiter based demodulator that work with low-IF receiver only. Yet, currently reported Ph-ADC based demodulator lack of preamble detection for BLE which will be used as symbol clock synchronization. In this work, a Ph-ADC based demodulator is proposed with the feature of preamble detection on BLE's packet. The detected preamble is used for symbol clock recovery and compensation of carrier frequency offset in a BLE packet. Besides, the proposed demodulator is flexible to demodulate IF or baseband signal by simply configuring a parameter value. Using MATLAB, minimum signal-to-noise Ratio (SNR) needed to demodulate BLE packet is estimated using Monte Carlo simulation with 99% confidence level. For hardware implementation, the proposed demodulator is implemented at RTL in Synopsys and its layout is generated using 0.18 μm CMOS technology. To understand the trade-off between power consumption, layout size and minimum SNR needed, the proposed Ph-ADC based demodulator is scaled to a different combination of 4-bit to 6-bit resolution and 2 MHz to 16 MHz sampling rate. Configuration with the best trade-off for the proposed Ph-ADC demodulator can achieve bit error rate (BER) of 0.1% at SNR of 12.5 dB and able to tolerate carrier frequency offset of ± 200 kHz while using only half the power needed by state of the art limiter based demodulator.
format	Article
author	Ung, Shen Jie Ab. Rahman, Ab. Al-Hadi
author_facet	Ung, Shen Jie Ab. Rahman, Ab. Al-Hadi
author_sort	Ung, Shen Jie
title	A 88 μW digital phase-domain GFSK demodulator compatible with low-if and zero-IF receiver with preamble detection for BLE
title_short	A 88 μW digital phase-domain GFSK demodulator compatible with low-if and zero-IF receiver with preamble detection for BLE
title_full	A 88 μW digital phase-domain GFSK demodulator compatible with low-if and zero-IF receiver with preamble detection for BLE
title_fullStr	A 88 μW digital phase-domain GFSK demodulator compatible with low-if and zero-IF receiver with preamble detection for BLE
title_full_unstemmed	A 88 μW digital phase-domain GFSK demodulator compatible with low-if and zero-IF receiver with preamble detection for BLE
title_sort	88 μw digital phase-domain gfsk demodulator compatible with low-if and zero-if receiver with preamble detection for ble
publisher	Turkiye Klinikleri
publishDate	2020
url	http://eprints.utm.my/id/eprint/93457/1/UngShenJie2020_A88uWDigitalPhaseDomain.pdf http://eprints.utm.my/id/eprint/93457/ http://dx.doi.org/10.3906/ELK-1912-155
_version_	1718926070816702464
score	13.211869

A 88 μW digital phase-domain GFSK demodulator compatible with low-if and zero-IF receiver with preamble detection for BLE

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