A 88 μW digital phase-domain GFSK demodulator compatible with low-if and zero-IF receiver with preamble detection for BLE
Unlike conventional analog-to-digital converter (ADC), phase-domain ADC (Ph-ADC) is more power efficient for the implementation of fully digital Gaussian frequency shift keying (GFSK) demodulator in bluetooth low energy (BLE). Besides, Ph-ADC based demodulator is flexible to pair with low-IF and zer...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Turkiye Klinikleri
2020
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/93457/1/UngShenJie2020_A88uWDigitalPhaseDomain.pdf http://eprints.utm.my/id/eprint/93457/ http://dx.doi.org/10.3906/ELK-1912-155 |
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| Summary: | Unlike conventional analog-to-digital converter (ADC), phase-domain ADC (Ph-ADC) is more power efficient for the implementation of fully digital Gaussian frequency shift keying (GFSK) demodulator in bluetooth low energy (BLE). Besides, Ph-ADC based demodulator is flexible to pair with low-IF and zero-IF receiver, opposed to limiter based demodulator that work with low-IF receiver only. Yet, currently reported Ph-ADC based demodulator lack of preamble detection for BLE which will be used as symbol clock synchronization. In this work, a Ph-ADC based demodulator is proposed with the feature of preamble detection on BLE's packet. The detected preamble is used for symbol clock recovery and compensation of carrier frequency offset in a BLE packet. Besides, the proposed demodulator is flexible to demodulate IF or baseband signal by simply configuring a parameter value. Using MATLAB, minimum signal-to-noise Ratio (SNR) needed to demodulate BLE packet is estimated using Monte Carlo simulation with 99% confidence level. For hardware implementation, the proposed demodulator is implemented at RTL in Synopsys and its layout is generated using 0.18 μm CMOS technology. To understand the trade-off between power consumption, layout size and minimum SNR needed, the proposed Ph-ADC based demodulator is scaled to a different combination of 4-bit to 6-bit resolution and 2 MHz to 16 MHz sampling rate. Configuration with the best trade-off for the proposed Ph-ADC demodulator can achieve bit error rate (BER) of 0.1% at SNR of 12.5 dB and able to tolerate carrier frequency offset of ± 200 kHz while using only half the power needed by state of the art limiter based demodulator. |
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