The design of 16X1 array photon counting circuit with brent-kung adder optimization
Farming involves sequence and processes of cultivating crops; among others are bush clearing, irrigation, and soil testing. The soil testing carried out manually by dissolving chemical reagent to form a color, then compared with a color chart is time consuming and error prone without quantitative va...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2020
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| Online Access: | http://eprints.utm.my/id/eprint/93011/1/AbubakarMohammedMSKE2020.pdf http://eprints.utm.my/id/eprint/93011/ http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:135916 |
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| Summary: | Farming involves sequence and processes of cultivating crops; among others are bush clearing, irrigation, and soil testing. The soil testing carried out manually by dissolving chemical reagent to form a color, then compared with a color chart is time consuming and error prone without quantitative value. Subsequent systems comprise spectrophotometer, general packet radio service (GPRS), artificial neural network (ANN), and raspberry pi based are expensive and slow. Another system has been developed based on field programmable gate array (FPGA) with capability to test one sample at a time. FPGA supports parallel computing, but it depends on the program written to synthesize the hardware. To tap this advantage, this study developed a design of FPGA based photon counting system, using 16 bits parallel adder (Brent Kung) algorithm. The developed system comprises 16 bits buffer, 16 bits adder, 16 bits parallel input serial output (PISO), and the clock divider circuit. The incoming signal stored in buffer and passed to parallel adder. The parallel adder passes the result to PISO and the clock divider was used to control the counting. The main advantage of the method is speed, the algorithm allows parallel computation, such that, it will be easily implemented in low cost FPGA module. The speed of the adder was achieved by making FPGA operate in parallel mode. To test the effectiveness of the proposed method, Verilog hardware description language was used to synthesize through Vivado suite by Xilinx and simulated under different condition by changing the samples signal with various degree of frequency. It was further verified with Synopsys. The superiority of the proposed method over the conventional is high frequency of 625 MHz in FPGA, 1190 MHz for Brent Kung integrated circuit (IC) and 1639 MHz for two stage pipeline Brent Kung integrated circuit with low power of 2 mW in gate levels. It is envisioning that the proposed method will be very useful in the implementation of high performance, low cost for not only soil nutrient measurement, but also for transforming other serial system to parallel system. |
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