Staff View: ASIC implementation and optimization of 16 bit SDRAM memory controller

ASIC implementation and optimization of 16 bit SDRAM memory controller

Last-level caches (LLC) often used to relay between the central processing unit (CPU) and the main memory. Most traditional processor used static-random-access-memory (SRAM) as the cache storage. Other technologies such as embedded dynamic-random-access-memory (eDRAM) and Synchronous Dynamic Random...

Full description

Saved in:

Bibliographic Details
Main Authors:	Alias, Nurul Ezaila, Ishaak, Suhaila, Koo, Jian Hong, Loong, Michael Peng Tan, Hamzah, Afiq, Abdul Wahab, Yasmin
Format:	Conference or Workshop Item
Published:	2020
Subjects:	TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/92583/ http://dx.doi.org/10.1109/ICSE49846.2020.9166869
Tags:	Add Tag No Tags, Be the first to tag this record!

id	my.utm.92583
record_format	eprints
spelling	my.utm.925832021-10-28T10:18:17Z http://eprints.utm.my/id/eprint/92583/ ASIC implementation and optimization of 16 bit SDRAM memory controller Alias, Nurul Ezaila Ishaak, Suhaila Koo, Jian Hong Loong, Michael Peng Tan Hamzah, Afiq Abdul Wahab, Yasmin TK Electrical engineering. Electronics Nuclear engineering Last-level caches (LLC) often used to relay between the central processing unit (CPU) and the main memory. Most traditional processor used static-random-access-memory (SRAM) as the cache storage. Other technologies such as embedded dynamic-random-access-memory (eDRAM) and Synchronous Dynamic Random Access Memory (SDRAM) have also been implemented to store the caches information. SDRAM able to achieve a higher data transfer rates than asynchronous Dynamic Random Access Memory (DRAM). A memory controller is needed to manage the data flow. However, today issue's is the speed of fetching data from memories is unable to cope up the processors' speed since processors are getting faster day by day. Beside the speed limitation, a high-speed memory controller will also consume high dynamic power. Due to this fact, an optimized memory controller is needed to reduce the dynamic power used by the memory controller. This work proposed a reduction of dynamic power of the memory controller by reducing the switching activities. The focus of this work is to implement the design in Application Specific Integrated Circuit (ASIC) with switching power optimization of clock gating method. The clock gating cell is implemented in DC while optimized in ICC. It is found that the clock gating method able to reduce the percentage of switching power to 23% with average clock toggle rate saving of 41.6%. Besides, the voltage drop in the power network is also less than 10% which is 44.4mV or 2.22%. This work has proved that implementing of clock gating in the design is able to reduce the switching power and dynamic power without sacrificed the clock frequency. 2020-07 Conference or Workshop Item PeerReviewed Alias, Nurul Ezaila and Ishaak, Suhaila and Koo, Jian Hong and Loong, Michael Peng Tan and Hamzah, Afiq and Abdul Wahab, Yasmin (2020) ASIC implementation and optimization of 16 bit SDRAM memory controller. In: 14th IEEE International Conference on Semiconductor Electronics, ICSE 2020, 28 July 2020 - 29 July 2020, Kuala Lumpur, Malaysia. http://dx.doi.org/10.1109/ICSE49846.2020.9166869
institution	Universiti Teknologi Malaysia
building	UTM Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Teknologi Malaysia
content_source	UTM Institutional Repository
url_provider	http://eprints.utm.my/
topic	TK Electrical engineering. Electronics Nuclear engineering
spellingShingle	TK Electrical engineering. Electronics Nuclear engineering Alias, Nurul Ezaila Ishaak, Suhaila Koo, Jian Hong Loong, Michael Peng Tan Hamzah, Afiq Abdul Wahab, Yasmin ASIC implementation and optimization of 16 bit SDRAM memory controller
description	Last-level caches (LLC) often used to relay between the central processing unit (CPU) and the main memory. Most traditional processor used static-random-access-memory (SRAM) as the cache storage. Other technologies such as embedded dynamic-random-access-memory (eDRAM) and Synchronous Dynamic Random Access Memory (SDRAM) have also been implemented to store the caches information. SDRAM able to achieve a higher data transfer rates than asynchronous Dynamic Random Access Memory (DRAM). A memory controller is needed to manage the data flow. However, today issue's is the speed of fetching data from memories is unable to cope up the processors' speed since processors are getting faster day by day. Beside the speed limitation, a high-speed memory controller will also consume high dynamic power. Due to this fact, an optimized memory controller is needed to reduce the dynamic power used by the memory controller. This work proposed a reduction of dynamic power of the memory controller by reducing the switching activities. The focus of this work is to implement the design in Application Specific Integrated Circuit (ASIC) with switching power optimization of clock gating method. The clock gating cell is implemented in DC while optimized in ICC. It is found that the clock gating method able to reduce the percentage of switching power to 23% with average clock toggle rate saving of 41.6%. Besides, the voltage drop in the power network is also less than 10% which is 44.4mV or 2.22%. This work has proved that implementing of clock gating in the design is able to reduce the switching power and dynamic power without sacrificed the clock frequency.
format	Conference or Workshop Item
author	Alias, Nurul Ezaila Ishaak, Suhaila Koo, Jian Hong Loong, Michael Peng Tan Hamzah, Afiq Abdul Wahab, Yasmin
author_facet	Alias, Nurul Ezaila Ishaak, Suhaila Koo, Jian Hong Loong, Michael Peng Tan Hamzah, Afiq Abdul Wahab, Yasmin
author_sort	Alias, Nurul Ezaila
title	ASIC implementation and optimization of 16 bit SDRAM memory controller
title_short	ASIC implementation and optimization of 16 bit SDRAM memory controller
title_full	ASIC implementation and optimization of 16 bit SDRAM memory controller
title_fullStr	ASIC implementation and optimization of 16 bit SDRAM memory controller
title_full_unstemmed	ASIC implementation and optimization of 16 bit SDRAM memory controller
title_sort	asic implementation and optimization of 16 bit sdram memory controller
publishDate	2020
url	http://eprints.utm.my/id/eprint/92583/ http://dx.doi.org/10.1109/ICSE49846.2020.9166869
_version_	1715189659338801152
score	13.211869

ASIC implementation and optimization of 16 bit SDRAM memory controller

Similar Items