ASIC implementation and optimization of 16 bit SDRAM memory controller
Last-level caches (LLC) often used to relay between the central processing unit (CPU) and the main memory. Most traditional processor used static-random-access-memory (SRAM) as the cache storage. Other technologies such as embedded dynamic-random-access-memory (eDRAM) and Synchronous Dynamic Random...
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| Main Authors: | , , , , , |
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| Format: | Conference or Workshop Item |
| Published: |
2020
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/92583/ http://dx.doi.org/10.1109/ICSE49846.2020.9166869 |
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