ASIC implementation and optimization of 16 bit SDRAM memory controller
Last-level caches (LLC) often used to relay between the central processing unit (CPU) and the main memory. Most traditional processor used static-random-access-memory (SRAM) as the cache storage. Other technologies such as embedded dynamic-random-access-memory (eDRAM) and Synchronous Dynamic Random...
保存先:
| 主要な著者: | , , , , , |
|---|---|
| フォーマット: | Conference or Workshop Item |
| 出版事項: |
2020
|
| 主題: | |
| オンライン･アクセス: | http://eprints.utm.my/id/eprint/92583/ http://dx.doi.org/10.1109/ICSE49846.2020.9166869 |
| タグ: |
タグ追加
タグなし, このレコードへの初めてのタグを付けませんか!
|
| 要約: | Last-level caches (LLC) often used to relay between the central processing unit (CPU) and the main memory. Most traditional processor used static-random-access-memory (SRAM) as the cache storage. Other technologies such as embedded dynamic-random-access-memory (eDRAM) and Synchronous Dynamic Random Access Memory (SDRAM) have also been implemented to store the caches information. SDRAM able to achieve a higher data transfer rates than asynchronous Dynamic Random Access Memory (DRAM). A memory controller is needed to manage the data flow. However, today issue's is the speed of fetching data from memories is unable to cope up the processors' speed since processors are getting faster day by day. Beside the speed limitation, a high-speed memory controller will also consume high dynamic power. Due to this fact, an optimized memory controller is needed to reduce the dynamic power used by the memory controller. This work proposed a reduction of dynamic power of the memory controller by reducing the switching activities. The focus of this work is to implement the design in Application Specific Integrated Circuit (ASIC) with switching power optimization of clock gating method. The clock gating cell is implemented in DC while optimized in ICC. It is found that the clock gating method able to reduce the percentage of switching power to 23% with average clock toggle rate saving of 41.6%. Besides, the voltage drop in the power network is also less than 10% which is 44.4mV or 2.22%. This work has proved that implementing of clock gating in the design is able to reduce the switching power and dynamic power without sacrificed the clock frequency. |
|---|