An integrated DFT solution for power reduction in scan test applications by low power gating scan cell
Shrinking technologies to deep sub-microns has raised demands for high quality testing. However, excessive power during test application time serves as limiting factors for reliability in testing. To address these issues, we have proposed Integrated Low Power Gating (ILPG) Scan Cell to alleviate shi...
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| Main Authors: | , , , , |
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| Format: | Article |
| Published: |
Elsevier B.V.
2017
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/76294/ https://www.scopus.com/inward/record.uri?eid=2-s2.0-85006141152&doi=10.1016%2fj.vlsi.2016.12.009&partnerID=40&md5=dc5ddb85179face99193d49926932463 |
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