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Built-in self test power and test time analysis in on-chip networks

Testing power dissipation of on-chip networks (NoC) is an interesting topic, which is still unexplored specially analytically. In this paper, a transistor level model is proposed to study the testing power and area of testing logic in a mesh NoC using IEEE 1149.1-based approach. For the purpose of v...

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Main Authors: Senejani, Mahdieh Nadi, Ghadiry, Mahdiar, Chia, Yee Ooi, Marsono, Muhammad Nadzir
Format: Article
Published: Springer Science+Business Media New York 2015
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utm.my/id/eprint/57990/
http://dx.doi.org/10.1007/s00034-014-9892-4
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spelling my.utm.579902021-08-03T07:28:52Z http://eprints.utm.my/id/eprint/57990/ Built-in self test power and test time analysis in on-chip networks Senejani, Mahdieh Nadi Ghadiry, Mahdiar Chia, Yee Ooi Marsono, Muhammad Nadzir TK Electrical engineering. Electronics Nuclear engineering Testing power dissipation of on-chip networks (NoC) is an interesting topic, which is still unexplored specially analytically. In this paper, a transistor level model is proposed to study the testing power and area of testing logic in a mesh NoC using IEEE 1149.1-based approach. For the purpose of verification, HSPICE simulation and FPGA implementation are used. The switching activities are computed using a special purpose cycle-accurate NoC simulator. At the end, the model is used to calculate test power and spot the most energy consuming and area occupying component of a typical NoC testing circuit. Springer Science+Business Media New York 2015-04 Article PeerReviewed Senejani, Mahdieh Nadi and Ghadiry, Mahdiar and Chia, Yee Ooi and Marsono, Muhammad Nadzir (2015) Built-in self test power and test time analysis in on-chip networks. Circuits, Systems, And Signal Processing, 34 (4). pp. 1057-1075. ISSN 0278-081X http://dx.doi.org/10.1007/s00034-014-9892-4 DOI:10.1007/s00034-014-9892-4
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Senejani, Mahdieh Nadi
Ghadiry, Mahdiar
Chia, Yee Ooi
Marsono, Muhammad Nadzir
Built-in self test power and test time analysis in on-chip networks
description Testing power dissipation of on-chip networks (NoC) is an interesting topic, which is still unexplored specially analytically. In this paper, a transistor level model is proposed to study the testing power and area of testing logic in a mesh NoC using IEEE 1149.1-based approach. For the purpose of verification, HSPICE simulation and FPGA implementation are used. The switching activities are computed using a special purpose cycle-accurate NoC simulator. At the end, the model is used to calculate test power and spot the most energy consuming and area occupying component of a typical NoC testing circuit.
format Article
author Senejani, Mahdieh Nadi
Ghadiry, Mahdiar
Chia, Yee Ooi
Marsono, Muhammad Nadzir
author_facet Senejani, Mahdieh Nadi
Ghadiry, Mahdiar
Chia, Yee Ooi
Marsono, Muhammad Nadzir
author_sort Senejani, Mahdieh Nadi
title Built-in self test power and test time analysis in on-chip networks
title_short Built-in self test power and test time analysis in on-chip networks
title_full Built-in self test power and test time analysis in on-chip networks
title_fullStr Built-in self test power and test time analysis in on-chip networks
title_full_unstemmed Built-in self test power and test time analysis in on-chip networks
title_sort built-in self test power and test time analysis in on-chip networks
publisher Springer Science+Business Media New York
publishDate 2015
url http://eprints.utm.my/id/eprint/57990/
http://dx.doi.org/10.1007/s00034-014-9892-4
_version_ 1707765835948359680
score 13.211869

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