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Hardware/software system-on-chip co-verification platform based on logic-based environment for application programming interfacing

System-on-chip (SoC) is a single-chip that integrates hardware and software components. Hardware/software co-design and co-verification are crucial steps to ensure functional correctness of SoC design. Hardware/software co-verification technique is needed to test and decide ways to partition softwar...

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Main Author: Teo, Hong Yap
Format: Thesis
Language:English
Published: 2015
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utm.my/id/eprint/53896/1/TeoHongYapMFKE2015.pdf
http://eprints.utm.my/id/eprint/53896/
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spelling my.utm.538962020-10-08T01:41:26Z http://eprints.utm.my/id/eprint/53896/ Hardware/software system-on-chip co-verification platform based on logic-based environment for application programming interfacing Teo, Hong Yap TK Electrical engineering. Electronics Nuclear engineering System-on-chip (SoC) is a single-chip that integrates hardware and software components. Hardware/software co-design and co-verification are crucial steps to ensure functional correctness of SoC design. Hardware/software co-verification technique is needed to test and decide ways to partition software and hardware components for an optimized system. Recently, field-programmable gate array (FPGA) prototyping has been proposed as a method that provides a rapid prototyping platform of SoC development and verification. SoC FPGA prototyping involves multiple cross-platform asynchronous clock domains that make SoC verification process becomes more challenging. This project implements an asynchronous firstin- first-out (FIFO) based data transfer between two hardware components which are operating in different clock domains. This implementation operates in actual FPGA and makes use of Logic-based Environment for Application Programming (LEAP) infrastructure such as communication mechanism to allow communication between hardware and software models or components. A study related to execution time characterization is done to understand the effects of hardware/software tasks partitioning on hardware/software communication, hardware execution and software execution time. Resource analysis is done on asynchronous FIFO implementation and it shows a logarithmic relationship between the logic elements and FIFO entries. An approximately linear relationship between two-way average latency and data size are shown by passing data from FPGA to host and return back the data from host to FPGA. MPEG-2 Audio Layer III (MP3) decoder case study shows with an optimum hardware/software partitioning, the co-verification platform is able to achieve a communication time of approximately 30 million cycles with 99.99 percent of the time spent originated from hardware/software communication. This result clearly shows that bidirectional communication between hardware and software plays a significant role in affecting the total communication time spent for particular application which has tasks running in both hardware and software. 2015-06 Thesis NonPeerReviewed application/pdf en http://eprints.utm.my/id/eprint/53896/1/TeoHongYapMFKE2015.pdf Teo, Hong Yap (2015) Hardware/software system-on-chip co-verification platform based on logic-based environment for application programming interfacing. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering. http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:86428
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
language English
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Teo, Hong Yap
Hardware/software system-on-chip co-verification platform based on logic-based environment for application programming interfacing
description System-on-chip (SoC) is a single-chip that integrates hardware and software components. Hardware/software co-design and co-verification are crucial steps to ensure functional correctness of SoC design. Hardware/software co-verification technique is needed to test and decide ways to partition software and hardware components for an optimized system. Recently, field-programmable gate array (FPGA) prototyping has been proposed as a method that provides a rapid prototyping platform of SoC development and verification. SoC FPGA prototyping involves multiple cross-platform asynchronous clock domains that make SoC verification process becomes more challenging. This project implements an asynchronous firstin- first-out (FIFO) based data transfer between two hardware components which are operating in different clock domains. This implementation operates in actual FPGA and makes use of Logic-based Environment for Application Programming (LEAP) infrastructure such as communication mechanism to allow communication between hardware and software models or components. A study related to execution time characterization is done to understand the effects of hardware/software tasks partitioning on hardware/software communication, hardware execution and software execution time. Resource analysis is done on asynchronous FIFO implementation and it shows a logarithmic relationship between the logic elements and FIFO entries. An approximately linear relationship between two-way average latency and data size are shown by passing data from FPGA to host and return back the data from host to FPGA. MPEG-2 Audio Layer III (MP3) decoder case study shows with an optimum hardware/software partitioning, the co-verification platform is able to achieve a communication time of approximately 30 million cycles with 99.99 percent of the time spent originated from hardware/software communication. This result clearly shows that bidirectional communication between hardware and software plays a significant role in affecting the total communication time spent for particular application which has tasks running in both hardware and software.
format Thesis
author Teo, Hong Yap
author_facet Teo, Hong Yap
author_sort Teo, Hong Yap
title Hardware/software system-on-chip co-verification platform based on logic-based environment for application programming interfacing
title_short Hardware/software system-on-chip co-verification platform based on logic-based environment for application programming interfacing
title_full Hardware/software system-on-chip co-verification platform based on logic-based environment for application programming interfacing
title_fullStr Hardware/software system-on-chip co-verification platform based on logic-based environment for application programming interfacing
title_full_unstemmed Hardware/software system-on-chip co-verification platform based on logic-based environment for application programming interfacing
title_sort hardware/software system-on-chip co-verification platform based on logic-based environment for application programming interfacing
publishDate 2015
url http://eprints.utm.my/id/eprint/53896/1/TeoHongYapMFKE2015.pdf
http://eprints.utm.my/id/eprint/53896/
http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:86428
_version_ 1681489446886703104
score 13.211869

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