Hardware/software system-on-chip co-verification platform based on logic-based environment for application programming interfacing
System-on-chip (SoC) is a single-chip that integrates hardware and software components. Hardware/software co-design and co-verification are crucial steps to ensure functional correctness of SoC design. Hardware/software co-verification technique is needed to test and decide ways to partition softwar...
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis |
| Language: | English |
| Published: |
2015
|
| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/53896/1/TeoHongYapMFKE2015.pdf http://eprints.utm.my/id/eprint/53896/ http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:86428 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | System-on-chip (SoC) is a single-chip that integrates hardware and software components. Hardware/software co-design and co-verification are crucial steps to ensure functional correctness of SoC design. Hardware/software co-verification technique is needed to test and decide ways to partition software and hardware components for an optimized system. Recently, field-programmable gate array (FPGA) prototyping has been proposed as a method that provides a rapid prototyping platform of SoC development and verification. SoC FPGA prototyping involves multiple cross-platform asynchronous clock domains that make SoC verification process becomes more challenging. This project implements an asynchronous firstin- first-out (FIFO) based data transfer between two hardware components which are operating in different clock domains. This implementation operates in actual FPGA and makes use of Logic-based Environment for Application Programming (LEAP) infrastructure such as communication mechanism to allow communication between hardware and software models or components. A study related to execution time characterization is done to understand the effects of hardware/software tasks partitioning on hardware/software communication, hardware execution and software execution time. Resource analysis is done on asynchronous FIFO implementation and it shows a logarithmic relationship between the logic elements and FIFO entries. An approximately linear relationship between two-way average latency and data size are shown by passing data from FPGA to host and return back the data from host to FPGA. MPEG-2 Audio Layer III (MP3) decoder case study shows with an optimum hardware/software partitioning, the co-verification platform is able to achieve a communication time of approximately 30 million cycles with 99.99 percent of the time spent originated from hardware/software communication. This result clearly shows that bidirectional communication between hardware and software plays a significant role in affecting the total communication time spent for particular application which has tasks running in both hardware and software. |
|---|