Second-stage tuning procedure for analogue CMOS design reuse methodology
Proposed is a two-stage analogue circuit design reuse methodology by extending existing fabrication process rescaling procedures with a follow-on systematic tuning procedure stage based on DC output voltage scaling. It increases the potential for design reuse with short-channel MOSFET circuit design...
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| Main Authors: | , , , , |
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| Format: | Article |
| Published: |
The Institution of Engineering and Technology
2012
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/33500/ https://ieeexplore.ieee.org/document/6260051 |
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