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Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm

The current semiconductor technology allows integration of all components onto a single chip called system-on-chip (SoC), which scales down the size of product and improves the performance. When a system becomes more complicated, testing process, such as test scheduling, becomes more challenging. Re...

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Main Authors: Chia, Yee Ooi, Jia, Pao Sua, Siaw, Chen Lee
Format: Article
Published: Elsevier 2012
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utm.my/id/eprint/33467/
http://dx.doi.org/10.1016/j.compeleceng.2012.04.010
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spelling my.utm.334672018-11-30T06:35:36Z http://eprints.utm.my/id/eprint/33467/ Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm Chia, Yee Ooi Jia, Pao Sua Siaw, Chen Lee TK Electrical engineering. Electronics Nuclear engineering The current semiconductor technology allows integration of all components onto a single chip called system-on-chip (SoC), which scales down the size of product and improves the performance. When a system becomes more complicated, testing process, such as test scheduling, becomes more challenging. Recently, peak power has also been considered as constraints in the test scheduling problem. Besides these constraints, some add-on techniques including pre-emption and non-consecutive test bus assignment have been introduced. The main contribution of each technique is the reduction of idling time in the test scheduling and thus reducing the total test time. This paper proposes a power-aware test scheduling called enhanced rectangle packing (ERP). In this technique, we formulate the test scheduling problem as the rectangle packing with horizontally and vertically split-able items (rectangles) which are smaller to fill up more compactly the test scheduling floor plan. Experimental results conducted on ITC'02 SoC benchmark circuits revealed positive improvement of the power-aware ERP algorithm in reducing total SoC test time. Elsevier 2012-11 Article PeerReviewed Chia, Yee Ooi and Jia, Pao Sua and Siaw, Chen Lee (2012) Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm. Computers and Electrical Engineering, 38 (6). pp. 1444-1455. ISSN 0045-7906 http://dx.doi.org/10.1016/j.compeleceng.2012.04.010 DOI:10.1016/j.compeleceng.2012.04.010
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Chia, Yee Ooi
Jia, Pao Sua
Siaw, Chen Lee
Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm
description The current semiconductor technology allows integration of all components onto a single chip called system-on-chip (SoC), which scales down the size of product and improves the performance. When a system becomes more complicated, testing process, such as test scheduling, becomes more challenging. Recently, peak power has also been considered as constraints in the test scheduling problem. Besides these constraints, some add-on techniques including pre-emption and non-consecutive test bus assignment have been introduced. The main contribution of each technique is the reduction of idling time in the test scheduling and thus reducing the total test time. This paper proposes a power-aware test scheduling called enhanced rectangle packing (ERP). In this technique, we formulate the test scheduling problem as the rectangle packing with horizontally and vertically split-able items (rectangles) which are smaller to fill up more compactly the test scheduling floor plan. Experimental results conducted on ITC'02 SoC benchmark circuits revealed positive improvement of the power-aware ERP algorithm in reducing total SoC test time.
format Article
author Chia, Yee Ooi
Jia, Pao Sua
Siaw, Chen Lee
author_facet Chia, Yee Ooi
Jia, Pao Sua
Siaw, Chen Lee
author_sort Chia, Yee Ooi
title Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm
title_short Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm
title_full Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm
title_fullStr Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm
title_full_unstemmed Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm
title_sort power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm
publisher Elsevier
publishDate 2012
url http://eprints.utm.my/id/eprint/33467/
http://dx.doi.org/10.1016/j.compeleceng.2012.04.010
_version_ 1643649339846819840
score 13.211869

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