Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm
The current semiconductor technology allows integration of all components onto a single chip called system-on-chip (SoC), which scales down the size of product and improves the performance. When a system becomes more complicated, testing process, such as test scheduling, becomes more challenging. Re...
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| Main Authors: | , , |
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| Format: | Article |
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Elsevier
2012
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/33467/ http://dx.doi.org/10.1016/j.compeleceng.2012.04.010 |
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