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Design for testability I: from full scan to partial scan

It is important to check whether the manufactured circuit has physical defects or not. Else, the defective part may adversely affect the circuit's functioning. The checking process is called testing or manufacturing test. In other words, manufacturing test is an important step in VLSI realizati...

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Main Author: Chia, Yee Ooi
Format: Book Section
Language:English
Published: Penerbit UTM 2008
Subjects:
T Technology (General)
Online Access:http://eprints.utm.my/id/eprint/31036/1/ChiaYeeOoi2008_DesignforTestabilityIFromFullScantoPartial.pdf
http://eprints.utm.my/id/eprint/31036/
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spelling my.utm.310362017-08-03T00:43:48Z http://eprints.utm.my/id/eprint/31036/ Design for testability I: from full scan to partial scan Chia, Yee Ooi T Technology (General) It is important to check whether the manufactured circuit has physical defects or not. Else, the defective part may adversely affect the circuit's functioning. The checking process is called testing or manufacturing test. In other words, manufacturing test is an important step in VLSI realization process. Figure 6.1 shows the process. As can be seen in Figure 6.1, there is a stage called test development where it basically consists of three activities; test generation, fault simulation and design for testability implementation. Test generation is a method of generating an input sequence that can distinguish between good chip and defective chip when the input sequence (test sequence) is applied to the chip using a tester. Fault simulation is a step of simulating circuits in the presence of faults. This step is used to evaluate the quality of a set of test sequence by indicating the fault coverage of the test sequence applied to a circuit. Penerbit UTM 2008 Book Section PeerReviewed application/pdf en http://eprints.utm.my/id/eprint/31036/1/ChiaYeeOoi2008_DesignforTestabilityIFromFullScantoPartial.pdf Chia, Yee Ooi (2008) Design for testability I: from full scan to partial scan. In: Advances In Microelectronics. Penerbit UTM, Skudai, Johor Bahru, pp. 94-121. ISBN 978-983-52-0654-2
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
language English
topic T Technology (General)
spellingShingle T Technology (General)
Chia, Yee Ooi
Design for testability I: from full scan to partial scan
description It is important to check whether the manufactured circuit has physical defects or not. Else, the defective part may adversely affect the circuit's functioning. The checking process is called testing or manufacturing test. In other words, manufacturing test is an important step in VLSI realization process. Figure 6.1 shows the process. As can be seen in Figure 6.1, there is a stage called test development where it basically consists of three activities; test generation, fault simulation and design for testability implementation. Test generation is a method of generating an input sequence that can distinguish between good chip and defective chip when the input sequence (test sequence) is applied to the chip using a tester. Fault simulation is a step of simulating circuits in the presence of faults. This step is used to evaluate the quality of a set of test sequence by indicating the fault coverage of the test sequence applied to a circuit.
format Book Section
author Chia, Yee Ooi
author_facet Chia, Yee Ooi
author_sort Chia, Yee Ooi
title Design for testability I: from full scan to partial scan
title_short Design for testability I: from full scan to partial scan
title_full Design for testability I: from full scan to partial scan
title_fullStr Design for testability I: from full scan to partial scan
title_full_unstemmed Design for testability I: from full scan to partial scan
title_sort design for testability i: from full scan to partial scan
publisher Penerbit UTM
publishDate 2008
url http://eprints.utm.my/id/eprint/31036/1/ChiaYeeOoi2008_DesignforTestabilityIFromFullScantoPartial.pdf
http://eprints.utm.my/id/eprint/31036/
_version_ 1643648652279808000
score 13.211869

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