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A secure field programmable gate array based system-on-chip for telemedicine application

In Telemedicine, confidential information is transferred through an unsecure channel from one party to another. In this paper, a field programmable gate array (FPGA) based approach to protect the data in the Telemedicine system, the mySECURE II is developed. There are two security schemes on a crypt...

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Main Authors: N. M., Thamrin, I., Ahmad, Mohd. Hani, Mohamed Khalil
Format: Book Section
Published: IEEE Explorer 2011
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utm.my/id/eprint/28636/
http://ieeexplore.ieee.org/document/5978518/
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spelling my.utm.286362017-06-14T03:50:23Z http://eprints.utm.my/id/eprint/28636/ A secure field programmable gate array based system-on-chip for telemedicine application N. M., Thamrin I., Ahmad Mohd. Hani, Mohamed Khalil TK Electrical engineering. Electronics Nuclear engineering In Telemedicine, confidential information is transferred through an unsecure channel from one party to another. In this paper, a field programmable gate array (FPGA) based approach to protect the data in the Telemedicine system, the mySECURE II is developed. There are two security schemes on a crypto System-on-Chip (SoC) proposed in this paper namely hybrid encryption scheme and Rivest-Shamir-Adleman (RSA) based digital signature scheme. It focuses on the development of 128-bit Advanced Encryption Standard (AES) subsystem, 2048-bit RSA crypto subsystem and Secure Hash Algorithm (SHA-1) crypto subsystem. In AES encryption and RSA crypto subsystems, the strength of these cryptosystems relies on keys. Therefore, a hybrid random number generator (RNG) is designed to provide on-chip key generation operation in this work. The crypto SOC is designed using hardware-software codesign technique. The hardware subsystems design are implemented on Altera Stratix 1S40F780C5 FPGA development board and integrated with Nios II processor to form a complete cryptosystem in System of Programmable Chip (SoPC) environment. The software design consists of the development of device drivers for hardware subsystem communication, and implementation of Cryptographic Service Provider (CSP), serves as the Application Programming Interface (API) in host PC. As a result, a prototype has been developed to test the functionality of the crypto hardware subsystem as well as the usability of the CSP. IEEE Explorer 2011 Book Section PeerReviewed N. M., Thamrin and I., Ahmad and Mohd. Hani, Mohamed Khalil (2011) A secure field programmable gate array based system-on-chip for telemedicine application. In: International Conference on Information Society, i-Society 2011. IEEE Explorer, pp. 105-109. ISBN 978-095642638-3 http://ieeexplore.ieee.org/document/5978518/
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
N. M., Thamrin
I., Ahmad
Mohd. Hani, Mohamed Khalil
A secure field programmable gate array based system-on-chip for telemedicine application
description In Telemedicine, confidential information is transferred through an unsecure channel from one party to another. In this paper, a field programmable gate array (FPGA) based approach to protect the data in the Telemedicine system, the mySECURE II is developed. There are two security schemes on a crypto System-on-Chip (SoC) proposed in this paper namely hybrid encryption scheme and Rivest-Shamir-Adleman (RSA) based digital signature scheme. It focuses on the development of 128-bit Advanced Encryption Standard (AES) subsystem, 2048-bit RSA crypto subsystem and Secure Hash Algorithm (SHA-1) crypto subsystem. In AES encryption and RSA crypto subsystems, the strength of these cryptosystems relies on keys. Therefore, a hybrid random number generator (RNG) is designed to provide on-chip key generation operation in this work. The crypto SOC is designed using hardware-software codesign technique. The hardware subsystems design are implemented on Altera Stratix 1S40F780C5 FPGA development board and integrated with Nios II processor to form a complete cryptosystem in System of Programmable Chip (SoPC) environment. The software design consists of the development of device drivers for hardware subsystem communication, and implementation of Cryptographic Service Provider (CSP), serves as the Application Programming Interface (API) in host PC. As a result, a prototype has been developed to test the functionality of the crypto hardware subsystem as well as the usability of the CSP.
format Book Section
author N. M., Thamrin
I., Ahmad
Mohd. Hani, Mohamed Khalil
author_facet N. M., Thamrin
I., Ahmad
Mohd. Hani, Mohamed Khalil
author_sort N. M., Thamrin
title A secure field programmable gate array based system-on-chip for telemedicine application
title_short A secure field programmable gate array based system-on-chip for telemedicine application
title_full A secure field programmable gate array based system-on-chip for telemedicine application
title_fullStr A secure field programmable gate array based system-on-chip for telemedicine application
title_full_unstemmed A secure field programmable gate array based system-on-chip for telemedicine application
title_sort secure field programmable gate array based system-on-chip for telemedicine application
publisher IEEE Explorer
publishDate 2011
url http://eprints.utm.my/id/eprint/28636/
http://ieeexplore.ieee.org/document/5978518/
_version_ 1643648119984881664
score 13.211869

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