A secure field programmable gate array based system-on-chip for telemedicine application

In Telemedicine, confidential information is transferred through an unsecure channel from one party to another. In this paper, a field programmable gate array (FPGA) based approach to protect the data in the Telemedicine system, the mySECURE II is developed. There are two security schemes on a crypt...

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Bibliographic Details
Main Authors: N. M., Thamrin, I., Ahmad, Mohd. Hani, Mohamed Khalil
Format: Book Section
Published: IEEE Explorer 2011
Subjects:
Online Access:http://eprints.utm.my/id/eprint/28636/
http://ieeexplore.ieee.org/document/5978518/
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Summary:In Telemedicine, confidential information is transferred through an unsecure channel from one party to another. In this paper, a field programmable gate array (FPGA) based approach to protect the data in the Telemedicine system, the mySECURE II is developed. There are two security schemes on a crypto System-on-Chip (SoC) proposed in this paper namely hybrid encryption scheme and Rivest-Shamir-Adleman (RSA) based digital signature scheme. It focuses on the development of 128-bit Advanced Encryption Standard (AES) subsystem, 2048-bit RSA crypto subsystem and Secure Hash Algorithm (SHA-1) crypto subsystem. In AES encryption and RSA crypto subsystems, the strength of these cryptosystems relies on keys. Therefore, a hybrid random number generator (RNG) is designed to provide on-chip key generation operation in this work. The crypto SOC is designed using hardware-software codesign technique. The hardware subsystems design are implemented on Altera Stratix 1S40F780C5 FPGA development board and integrated with Nios II processor to form a complete cryptosystem in System of Programmable Chip (SoPC) environment. The software design consists of the development of device drivers for hardware subsystem communication, and implementation of Cryptographic Service Provider (CSP), serves as the Application Programming Interface (API) in host PC. As a result, a prototype has been developed to test the functionality of the crypto hardware subsystem as well as the usability of the CSP.