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A new design-for-testability method based on thru-testability

Partial scan and non-scan techniques allow test generation of high fault coverage for sequential circuits with less area overhead and less performance degradation than full scan technique. In most of these techniques, extra logic (e.g. a multiplexer introduced by partial scan) is added to permit a d...

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Main Authors: Ooi, Chia Yee, Fujiwara, Hideo
Format: Article
Published: Springer Netherlands 2011
Subjects:
T Technology (General)
Online Access:http://eprints.utm.my/id/eprint/28586/
http://dx.doi.org/10.1007/s10836-011-5241-8
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spelling my.utm.285862019-01-28T03:35:23Z http://eprints.utm.my/id/eprint/28586/ A new design-for-testability method based on thru-testability Ooi, Chia Yee Fujiwara, Hideo T Technology (General) Partial scan and non-scan techniques allow test generation of high fault coverage for sequential circuits with less area overhead and less performance degradation than full scan technique. In most of these techniques, extra logic (e.g. a multiplexer introduced by partial scan) is added to permit a data transfer from a flip-flop (or input) to another flip-flop (or output). Such additional logic function is called thru function in this paper, which plays an essential role in enhancing the testability of a circuit. In this paper, we introduce a design-for-testability (DFT) technique which modifies a given sequential circuit to a thru-testable sequential circuit with acyclic test generation complexity by adding new thru functions based on the information of thru functions that may exist in the original design and the dependency among these thru functions. Thus, thru functions of a given sequential circuit should first be extracted from its high-level description. If there is a thru function that transfers data from a flip-flop to another flipflop, the latter is exempted from being considered in DFT insertion. This reduces the additional logic to be added. Using ITC'99 benchmark circuits, we show that the proposed DFT method takes up less area overhead compared to the previous scan methods in testing the difficult-to-test circuits like b07, b08 and b15. Besides, the test application time is shorter than that of previous scan methods while the test data volume is less too in difficult-to-test circuits. Springer Netherlands 2011-10 Article PeerReviewed Ooi, Chia Yee and Fujiwara, Hideo (2011) A new design-for-testability method based on thru-testability. Journal of Electronic Testing: Theory and Applications (JETTA), 27 (5). pp. 583-598. ISSN 1573-0727 http://dx.doi.org/10.1007/s10836-011-5241-8 DOI:10.1007/s10836-011-5241-8
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
topic T Technology (General)
spellingShingle T Technology (General)
Ooi, Chia Yee
Fujiwara, Hideo
A new design-for-testability method based on thru-testability
description Partial scan and non-scan techniques allow test generation of high fault coverage for sequential circuits with less area overhead and less performance degradation than full scan technique. In most of these techniques, extra logic (e.g. a multiplexer introduced by partial scan) is added to permit a data transfer from a flip-flop (or input) to another flip-flop (or output). Such additional logic function is called thru function in this paper, which plays an essential role in enhancing the testability of a circuit. In this paper, we introduce a design-for-testability (DFT) technique which modifies a given sequential circuit to a thru-testable sequential circuit with acyclic test generation complexity by adding new thru functions based on the information of thru functions that may exist in the original design and the dependency among these thru functions. Thus, thru functions of a given sequential circuit should first be extracted from its high-level description. If there is a thru function that transfers data from a flip-flop to another flipflop, the latter is exempted from being considered in DFT insertion. This reduces the additional logic to be added. Using ITC'99 benchmark circuits, we show that the proposed DFT method takes up less area overhead compared to the previous scan methods in testing the difficult-to-test circuits like b07, b08 and b15. Besides, the test application time is shorter than that of previous scan methods while the test data volume is less too in difficult-to-test circuits.
format Article
author Ooi, Chia Yee
Fujiwara, Hideo
author_facet Ooi, Chia Yee
Fujiwara, Hideo
author_sort Ooi, Chia Yee
title A new design-for-testability method based on thru-testability
title_short A new design-for-testability method based on thru-testability
title_full A new design-for-testability method based on thru-testability
title_fullStr A new design-for-testability method based on thru-testability
title_full_unstemmed A new design-for-testability method based on thru-testability
title_sort new design-for-testability method based on thru-testability
publisher Springer Netherlands
publishDate 2011
url http://eprints.utm.my/id/eprint/28586/
http://dx.doi.org/10.1007/s10836-011-5241-8
_version_ 1643648112076521472
score 13.211869

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