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Numerical simulation analysis of CMOS compatible process of 50nm vertical single and double gate MOSFET

Vertical MOSFET's have been proposed in the roadmap of semiconductor as a candidate for sub-100 nm CMOS technologies. In this paper, unique architecture of single and double gate vertical NMOS transistor is proposed that retained its CMOS compatibility. The MOSFET was fabricated by using obliqu...

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Main Authors:	Saad, Ismail, Ismail, Razali
Format:	Conference or Workshop Item
Published:	2007
Subjects:	TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/14249/
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spelling	my.utm.142492017-09-12T08:09:57Z http://eprints.utm.my/id/eprint/14249/ Numerical simulation analysis of CMOS compatible process of 50nm vertical single and double gate MOSFET Saad, Ismail Ismail, Razali TK Electrical engineering. Electronics Nuclear engineering Vertical MOSFET's have been proposed in the roadmap of semiconductor as a candidate for sub-100 nm CMOS technologies. In this paper, unique architecture of single and double gate vertical NMOS transistor is proposed that retained its CMOS compatibility. The MOSFET was fabricated by using oblique rotating ion implantation (ORI) technique addressed by numerical simulation. An electrical characterization of the device demonstrated a suppression of short channel effects (SCE) that was quantitatively given by an analysis of transfer and output characteristics with a reasonable value of threshold voltage (VT), drive and off -leakage current (ION and IOFF), saturation current (IDSat), subthreshold swing (S) and Drain Induced Barrier Lowering (DIBL). These results show that the vertical transistor is seen to offer considerable advantages down to the 100 nm node and beyond due to the dual or surround channels and the ability to produce a 50 nm channel length with relax lithography. 2007 Conference or Workshop Item PeerReviewed Saad, Ismail and Ismail, Razali (2007) Numerical simulation analysis of CMOS compatible process of 50nm vertical single and double gate MOSFET. In: International Coference on Advancement of Materials and Nanotechnology 2007 (ICAMN 2007), 2007, Langkawi.
institution	Universiti Teknologi Malaysia
building	UTM Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Teknologi Malaysia
content_source	UTM Institutional Repository
url_provider	http://eprints.utm.my/
topic	TK Electrical engineering. Electronics Nuclear engineering
spellingShingle	TK Electrical engineering. Electronics Nuclear engineering Saad, Ismail Ismail, Razali Numerical simulation analysis of CMOS compatible process of 50nm vertical single and double gate MOSFET
description	Vertical MOSFET's have been proposed in the roadmap of semiconductor as a candidate for sub-100 nm CMOS technologies. In this paper, unique architecture of single and double gate vertical NMOS transistor is proposed that retained its CMOS compatibility. The MOSFET was fabricated by using oblique rotating ion implantation (ORI) technique addressed by numerical simulation. An electrical characterization of the device demonstrated a suppression of short channel effects (SCE) that was quantitatively given by an analysis of transfer and output characteristics with a reasonable value of threshold voltage (VT), drive and off -leakage current (ION and IOFF), saturation current (IDSat), subthreshold swing (S) and Drain Induced Barrier Lowering (DIBL). These results show that the vertical transistor is seen to offer considerable advantages down to the 100 nm node and beyond due to the dual or surround channels and the ability to produce a 50 nm channel length with relax lithography.
format	Conference or Workshop Item
author	Saad, Ismail Ismail, Razali
author_facet	Saad, Ismail Ismail, Razali
author_sort	Saad, Ismail
title	Numerical simulation analysis of CMOS compatible process of 50nm vertical single and double gate MOSFET
title_short	Numerical simulation analysis of CMOS compatible process of 50nm vertical single and double gate MOSFET
title_full	Numerical simulation analysis of CMOS compatible process of 50nm vertical single and double gate MOSFET
title_fullStr	Numerical simulation analysis of CMOS compatible process of 50nm vertical single and double gate MOSFET
title_full_unstemmed	Numerical simulation analysis of CMOS compatible process of 50nm vertical single and double gate MOSFET
title_sort	numerical simulation analysis of cmos compatible process of 50nm vertical single and double gate mosfet
publishDate	2007
url	http://eprints.utm.my/id/eprint/14249/
_version_	1643646359400611840
score	13.211869

Numerical simulation analysis of CMOS compatible process of 50nm vertical single and double gate MOSFET

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