Efficient hardware-accelerated pseudoinverse computation through algorithm restructuring for parallelization in high-level synthesis
This paper describes a fast and efficient hardware-accelerated pseudoinverse computation through algorithm restructuring and leveraging FPGA synthesis directives for parallelism prior to high-level synthesis (HLS). The algorithm, which is composed of modified Gram–Schmidt QR decomposition (MGS-QRD),...
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| Main Authors: | , , , |
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| Format: | Article |
| Published: |
John Wiley and Sons Ltd
2022
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/101017/ http://dx.doi.org/10.1002/cta.3155 |
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