Low power 130 nm CMOS Johnson Counter with clock gating technique
In a very large scale integration (VLSI) of integrated circuit (IC) nowadays, digital circuit with low power design is the target of the IC designer. This is to prolong the battery life of the circuit especially if it is meant for wearable devices. In most of the digital circuits, counters are used...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
IOP Publishing
2018
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| Subjects: | |
| Online Access: | http://eprints.uthm.edu.my/2902/1/AJ%202019%20%2865%29.pdf http://eprints.uthm.edu.my/2902/ https://iopscience.iop.org/article/10.1088/1742-6596/1049/1/012073 |
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| Summary: | In a very large scale integration (VLSI) of integrated circuit (IC) nowadays, digital circuit with low power design is the target of the IC designer. This is to prolong the battery life of the circuit especially if it is meant for wearable devices. In most of the digital circuits, counters are used widely and these counters consumed a lot of power. Therefore in this project the reduction of power consumption of Johnson Counter by using clock gating technique is presented. Johnson Counter is used extensively to generate particular data and shift the data synchronously as per the output sequence of the counter. To ensure the power consumption is reduced, a clock gating technique is incorporated to the Johnson Counter. This counter is implemented in Cadence software using 130 nm Complementary Metal Oxide Semiconductor (CMOS) technology. The design is observed by comparing the design of a 4 bit Johnson Counter using clock gating technique and another 4 bit Johnson Counter without using the clock gating technique. The result shows the power consumption of the Johnson Counter using the clock gating technique is 21.22 μW while the regular Johnson Counter consumed 67.09 μW. Thus the power consumption is reduced by about 68.3% when a clock gating technique is used. |
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