Cost-Efficient Fault-Tolerant Decoder for Hybrid Nanoelectronic Memories
Existing work on fault tolerance in hybrid nanoelectronic memories (hybrid memories) assumes that faults only occur in the memory array and the encoder, not in the decoder. However, as the decoder is structured using scaled CMOS devices, it is also becoming vulnerable to faults. This paper present...
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| Main Authors: | , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2011
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| Subjects: | |
| Online Access: | http://eprints.utem.edu.my/id/eprint/4531/1/NZBHaron_DATE11.pdf http://eprints.utem.edu.my/id/eprint/4531/ |
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