Cost-Efficient Fault-Tolerant Decoder for Hybrid Nanoelectronic Memories
Existing work on fault tolerance in hybrid nanoelectronic memories (hybrid memories) assumes that faults only occur in the memory array and the encoder, not in the decoder. However, as the decoder is structured using scaled CMOS devices, it is also becoming vulnerable to faults. This paper present...
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2011
|
| Subjects: | |
| Online Access: | http://eprints.utem.edu.my/id/eprint/4531/1/NZBHaron_DATE11.pdf http://eprints.utem.edu.my/id/eprint/4531/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| id |
my.utem.eprints.4531 |
|---|---|
| record_format |
eprints |
| spelling |
my.utem.eprints.45312015-05-28T03:25:57Z http://eprints.utem.edu.my/id/eprint/4531/ Cost-Efficient Fault-Tolerant Decoder for Hybrid Nanoelectronic Memories Haron, Nor Zaidi Hamdioui, Said TK Electrical engineering. Electronics Nuclear engineering Existing work on fault tolerance in hybrid nanoelectronic memories (hybrid memories) assumes that faults only occur in the memory array and the encoder, not in the decoder. However, as the decoder is structured using scaled CMOS devices, it is also becoming vulnerable to faults. This paper presents a cost-efficient fault-tolerant decoder for hybrid memories that are impacted by a high degree of non-permanent clustered faults. Fault-tolerant capability is achieved by combining partial hardware redundancy scheme and on-line masking scheme based on Muller C-gates. In addition, the cost-efficient implementation of the decoder is realized by modifying the decoding sequence and implementing it based on time redundancy. Experimental results show that the proposed decoder is able to provide better reliability of the overall hybrid memory system, yet requires smaller area as compared to conventional decoder. For example, when assuming the fault ratio between decoder and memory array is 1:10 and at 10% fault rate, the proposed decoder ensures 1% higher reliability of the overall hybrid memory system. Moreover, the proposed decoder realizes 18.4% smaller area overhead for 64-bit word hybrid memory. 2011 Conference or Workshop Item PeerReviewed application/pdf en http://eprints.utem.edu.my/id/eprint/4531/1/NZBHaron_DATE11.pdf Haron, Nor Zaidi and Hamdioui, Said (2011) Cost-Efficient Fault-Tolerant Decoder for Hybrid Nanoelectronic Memories. In: Design, Automation & Test in Europe Conference , 14-18 March 2011, Grenoble, France. |
| institution |
Universiti Teknikal Malaysia Melaka |
| building |
UTEM Library |
| collection |
Institutional Repository |
| continent |
Asia |
| country |
Malaysia |
| content_provider |
Universiti Teknikal Malaysia Melaka |
| content_source |
UTEM Institutional Repository |
| url_provider |
http://eprints.utem.edu.my/ |
| language |
English |
| topic |
TK Electrical engineering. Electronics Nuclear engineering |
| spellingShingle |
TK Electrical engineering. Electronics Nuclear engineering Haron, Nor Zaidi Hamdioui, Said Cost-Efficient Fault-Tolerant Decoder for Hybrid Nanoelectronic Memories |
| description |
Existing work on fault tolerance in hybrid nanoelectronic
memories (hybrid memories) assumes that faults only occur in the memory array and the encoder, not in the decoder.
However, as the decoder is structured using scaled CMOS devices, it is also becoming vulnerable to faults. This paper presents a cost-efficient fault-tolerant decoder for hybrid memories that are impacted by a high degree of non-permanent clustered faults. Fault-tolerant capability is achieved by combining partial hardware redundancy scheme and on-line masking scheme based on Muller C-gates. In addition, the cost-efficient implementation of the decoder is realized by modifying the decoding sequence and implementing it based on time redundancy. Experimental
results show that the proposed decoder is able to provide better reliability of the overall hybrid memory system, yet requires smaller area as compared to conventional decoder. For example, when assuming the fault ratio between decoder and memory array is 1:10 and at 10% fault rate, the proposed decoder ensures 1% higher reliability of the overall hybrid memory system. Moreover, the proposed decoder realizes 18.4% smaller area overhead for 64-bit word hybrid memory. |
| format |
Conference or Workshop Item |
| author |
Haron, Nor Zaidi Hamdioui, Said |
| author_facet |
Haron, Nor Zaidi Hamdioui, Said |
| author_sort |
Haron, Nor Zaidi |
| title |
Cost-Efficient Fault-Tolerant Decoder for
Hybrid Nanoelectronic Memories |
| title_short |
Cost-Efficient Fault-Tolerant Decoder for
Hybrid Nanoelectronic Memories |
| title_full |
Cost-Efficient Fault-Tolerant Decoder for
Hybrid Nanoelectronic Memories |
| title_fullStr |
Cost-Efficient Fault-Tolerant Decoder for
Hybrid Nanoelectronic Memories |
| title_full_unstemmed |
Cost-Efficient Fault-Tolerant Decoder for
Hybrid Nanoelectronic Memories |
| title_sort |
cost-efficient fault-tolerant decoder for
hybrid nanoelectronic memories |
| publishDate |
2011 |
| url |
http://eprints.utem.edu.my/id/eprint/4531/1/NZBHaron_DATE11.pdf http://eprints.utem.edu.my/id/eprint/4531/ |
| _version_ |
1665905287961247744 |
| score |
13.211869 |