An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm
Combinatorial logic circuit minimization is usually done using Karnaugh’s Map or Boolean equation. This paper presents an application of Firefly Algorithm to design combinational logic circuit in which the objective function is to minimize the total number of gates used. Then, the algorithm is bench...
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| 主要な著者: | , , , , , , , |
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| フォーマット: | Conference or Workshop Item |
| 言語: | English |
| 出版事項: |
2014
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| 主題: | |
| オンライン･アクセス: | http://eprints.utem.edu.my/id/eprint/13783/1/004_CRUSC-17-21.pdf http://eprints.utem.edu.my/id/eprint/13783/ |
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