Design A High Performance Dual Ported 1 Read 1 Write CMOS SRAM
A synchronous dual-ported high speed and low power CMOS SRAM is described. This SRAM is an 8T (transistors) architecture that has 8 transistors in every single memory cell that are capable of performing a read and write operation in one cycle, under the condition that it is not performing the...
Saved in:
| Main Author: | |
|---|---|
| Format: | Monograph |
| Language: | English |
| Published: |
Universiti Sains Malaysia
2006
|
| Subjects: | |
| Online Access: | http://eprints.usm.my/58608/1/Design%20A%20High%20Performance%20Dual%20Ported%201%20Read%201%20Write%20CMOS%20SRAM_Yeoh%20Ee%20Ee.pdf http://eprints.usm.my/58608/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| id |
my.usm.eprints.58608 |
|---|---|
| record_format |
eprints |
| spelling |
my.usm.eprints.58608 http://eprints.usm.my/58608/ Design A High Performance Dual Ported 1 Read 1 Write CMOS SRAM Yeoh, Ee Ee T Technology TK Electrical Engineering. Electronics. Nuclear Engineering A synchronous dual-ported high speed and low power CMOS SRAM is described. This SRAM is an 8T (transistors) architecture that has 8 transistors in every single memory cell that are capable of performing a read and write operation in one cycle, under the condition that it is not performing the read and write operation in the same decoded address simultaneously. The proposed SRAM has 4Kbit memory capacity with 33 entries and 128 size of entry and was custom designed using 90nm process. The SRAM is operating properly with supply voltage of 1.05V. The targeted operating frequency is at 125MHz and it dissipates a maximum active power of 10.5mW and consumes a maximum standby power of 2.1mW. The targeted current consumption for the SRAM is having a maximum active value of 10mA and a maximum standby current of 2mA. The functionality of the SRAM is guaranteed by running simulations over a wide range of Process, Voltage and Temperature (PVT) corners. Internal race checking for SRAM has been adopted to perform further verification to ensure that there’s no failing signal in the SRAM that will cause functional error and excess power consumption in SRAM. Universiti Sains Malaysia 2006-05-01 Monograph NonPeerReviewed application/pdf en http://eprints.usm.my/58608/1/Design%20A%20High%20Performance%20Dual%20Ported%201%20Read%201%20Write%20CMOS%20SRAM_Yeoh%20Ee%20Ee.pdf Yeoh, Ee Ee (2006) Design A High Performance Dual Ported 1 Read 1 Write CMOS SRAM. Project Report. Universiti Sains Malaysia, Pusat Pengajian Kejuruteraan Elektrik dan Elektronik. (Submitted) |
| institution |
Universiti Sains Malaysia |
| building |
Hamzah Sendut Library |
| collection |
Institutional Repository |
| continent |
Asia |
| country |
Malaysia |
| content_provider |
Universiti Sains Malaysia |
| content_source |
USM Institutional Repository |
| url_provider |
http://eprints.usm.my/ |
| language |
English |
| topic |
T Technology TK Electrical Engineering. Electronics. Nuclear Engineering |
| spellingShingle |
T Technology TK Electrical Engineering. Electronics. Nuclear Engineering Yeoh, Ee Ee Design A High Performance Dual Ported 1 Read 1 Write CMOS SRAM |
| description |
A synchronous dual-ported high speed and low power CMOS SRAM is
described. This SRAM is an 8T (transistors) architecture that has 8 transistors in every
single memory cell that are capable of performing a read and write operation in one
cycle, under the condition that it is not performing the read and write operation in the
same decoded address simultaneously. The proposed SRAM has 4Kbit memory
capacity with 33 entries and 128 size of entry and was custom designed using 90nm
process. The SRAM is operating properly with supply voltage of 1.05V. The targeted
operating frequency is at 125MHz and it dissipates a maximum active power of
10.5mW and consumes a maximum standby power of 2.1mW. The targeted current
consumption for the SRAM is having a maximum active value of 10mA and a
maximum standby current of 2mA. The functionality of the SRAM is guaranteed by
running simulations over a wide range of Process, Voltage and Temperature (PVT)
corners. Internal race checking for SRAM has been adopted to perform further
verification to ensure that there’s no failing signal in the SRAM that will cause
functional error and excess power consumption in SRAM. |
| format |
Monograph |
| author |
Yeoh, Ee Ee |
| author_facet |
Yeoh, Ee Ee |
| author_sort |
Yeoh, Ee Ee |
| title |
Design A High Performance Dual Ported 1 Read 1 Write CMOS SRAM |
| title_short |
Design A High Performance Dual Ported 1 Read 1 Write CMOS SRAM |
| title_full |
Design A High Performance Dual Ported 1 Read 1 Write CMOS SRAM |
| title_fullStr |
Design A High Performance Dual Ported 1 Read 1 Write CMOS SRAM |
| title_full_unstemmed |
Design A High Performance Dual Ported 1 Read 1 Write CMOS SRAM |
| title_sort |
design a high performance dual ported 1 read 1 write cmos sram |
| publisher |
Universiti Sains Malaysia |
| publishDate |
2006 |
| url |
http://eprints.usm.my/58608/1/Design%20A%20High%20Performance%20Dual%20Ported%201%20Read%201%20Write%20CMOS%20SRAM_Yeoh%20Ee%20Ee.pdf http://eprints.usm.my/58608/ |
| _version_ |
1768007906632925184 |
| score |
13.211869 |