Design A High Performance Dual Ported 1 Read 1 Write CMOS SRAM
A synchronous dual-ported high speed and low power CMOS SRAM is described. This SRAM is an 8T (transistors) architecture that has 8 transistors in every single memory cell that are capable of performing a read and write operation in one cycle, under the condition that it is not performing the...
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| Main Author: | |
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| Format: | Monograph |
| Language: | English |
| Published: |
Universiti Sains Malaysia
2006
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| Subjects: | |
| Online Access: | http://eprints.usm.my/58608/1/Design%20A%20High%20Performance%20Dual%20Ported%201%20Read%201%20Write%20CMOS%20SRAM_Yeoh%20Ee%20Ee.pdf http://eprints.usm.my/58608/ |
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| Summary: | A synchronous dual-ported high speed and low power CMOS SRAM is
described. This SRAM is an 8T (transistors) architecture that has 8 transistors in every
single memory cell that are capable of performing a read and write operation in one
cycle, under the condition that it is not performing the read and write operation in the
same decoded address simultaneously. The proposed SRAM has 4Kbit memory
capacity with 33 entries and 128 size of entry and was custom designed using 90nm
process. The SRAM is operating properly with supply voltage of 1.05V. The targeted
operating frequency is at 125MHz and it dissipates a maximum active power of
10.5mW and consumes a maximum standby power of 2.1mW. The targeted current
consumption for the SRAM is having a maximum active value of 10mA and a
maximum standby current of 2mA. The functionality of the SRAM is guaranteed by
running simulations over a wide range of Process, Voltage and Temperature (PVT)
corners. Internal race checking for SRAM has been adopted to perform further
verification to ensure that there’s no failing signal in the SRAM that will cause
functional error and excess power consumption in SRAM. |
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