A Cost And Power Efficient Ddr4/Gddr5x/Gddr5 Transmitter With 3-Tap Equalizer
The demand on memory bandwidth has been increasing due to the rapid development in graphics intensive applications and big data analytics. Limited of the I/O and thermal densities, widening of data bus is no longer a feasible option for increasing memory bandwidth. Therefore, high-speed DDR transmit...
Saved in:
| 主要作者: | |
|---|---|
| 格式: | Thesis |
| 語言: | English |
| 出版: |
2016
|
| 主題: | |
| 在線閱讀: | http://eprints.usm.my/41304/1/NG_HOONG_CHIN_24_Pages.pdf http://eprints.usm.my/41304/ |
| 標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|