Cover Image

A Cost And Power Efficient Ddr4/Gddr5x/Gddr5 Transmitter With 3-Tap Equalizer

The demand on memory bandwidth has been increasing due to the rapid development in graphics intensive applications and big data analytics. Limited of the I/O and thermal densities, widening of data bus is no longer a feasible option for increasing memory bandwidth. Therefore, high-speed DDR transmit...

Full description

Saved in:
Bibliographic Details
Main Author: Ng , Hoong Chin
Format: Thesis
Language:English
Published: 2016
Subjects:
TK7800-8360 Electronics
Online Access:http://eprints.usm.my/41304/1/NG_HOONG_CHIN_24_Pages.pdf
http://eprints.usm.my/41304/
Tags: Add Tag
No Tags, Be the first to tag this record!
id my.usm.eprints.41304
record_format eprints
spelling my.usm.eprints.41304 http://eprints.usm.my/41304/ A Cost And Power Efficient Ddr4/Gddr5x/Gddr5 Transmitter With 3-Tap Equalizer Ng , Hoong Chin TK7800-8360 Electronics The demand on memory bandwidth has been increasing due to the rapid development in graphics intensive applications and big data analytics. Limited of the I/O and thermal densities, widening of data bus is no longer a feasible option for increasing memory bandwidth. Therefore, high-speed DDR transmitter is the current solution to the increasing demand on memory bandwidth until the through-silicon via technology is matured for 3D integration of memory modules. At high data rate, the channel losses at interconnect have necessitated the equalization on transmitting signal that will incur extra power and area to the transmitter. Achieving low cost and low power has become the greatest challenge in the design of transmitter with equalizer. For this objective, novel driver architecture in hybrid coding scheme was introduced to reduce pre-driver and routing resources. In concert with dual-function pre-driver cells, 3-tap equalization was achieved by manipulating the driver impedance code in a low power ALU. The proposed transmitter has achieved 6.4 Gb/s transmit rate in DDR4 standard with 40 % frequency margin, 10.0 Gb/s transmit rate in DDR5X standard with 5 % frequency margin and 8.0 Gb/s transmit rate in DDR5 standard with 15 % frequency margin. It has a size of 1175 um2 and an energy efficiency of 1.1 pJ/bit at 10 Gb/s GDDR5X interface, which is 50 % lower in power and 35 % lower in area cost when comparing against the power and area cost of the related works. The hybrid-coded driver with ALU-controlled equalizer demonstrates a viable solution to a cost and power efficiency transmitter for DDR4, GDDR5X and GDDR5 standards. 2016 Thesis NonPeerReviewed application/pdf en http://eprints.usm.my/41304/1/NG_HOONG_CHIN_24_Pages.pdf Ng , Hoong Chin (2016) A Cost And Power Efficient Ddr4/Gddr5x/Gddr5 Transmitter With 3-Tap Equalizer. Masters thesis, Universiti Sains Malaysia.
institution Universiti Sains Malaysia
building Hamzah Sendut Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Sains Malaysia
content_source USM Institutional Repository
url_provider http://eprints.usm.my/
language English
topic TK7800-8360 Electronics
spellingShingle TK7800-8360 Electronics
Ng , Hoong Chin
A Cost And Power Efficient Ddr4/Gddr5x/Gddr5 Transmitter With 3-Tap Equalizer
description The demand on memory bandwidth has been increasing due to the rapid development in graphics intensive applications and big data analytics. Limited of the I/O and thermal densities, widening of data bus is no longer a feasible option for increasing memory bandwidth. Therefore, high-speed DDR transmitter is the current solution to the increasing demand on memory bandwidth until the through-silicon via technology is matured for 3D integration of memory modules. At high data rate, the channel losses at interconnect have necessitated the equalization on transmitting signal that will incur extra power and area to the transmitter. Achieving low cost and low power has become the greatest challenge in the design of transmitter with equalizer. For this objective, novel driver architecture in hybrid coding scheme was introduced to reduce pre-driver and routing resources. In concert with dual-function pre-driver cells, 3-tap equalization was achieved by manipulating the driver impedance code in a low power ALU. The proposed transmitter has achieved 6.4 Gb/s transmit rate in DDR4 standard with 40 % frequency margin, 10.0 Gb/s transmit rate in DDR5X standard with 5 % frequency margin and 8.0 Gb/s transmit rate in DDR5 standard with 15 % frequency margin. It has a size of 1175 um2 and an energy efficiency of 1.1 pJ/bit at 10 Gb/s GDDR5X interface, which is 50 % lower in power and 35 % lower in area cost when comparing against the power and area cost of the related works. The hybrid-coded driver with ALU-controlled equalizer demonstrates a viable solution to a cost and power efficiency transmitter for DDR4, GDDR5X and GDDR5 standards.
format Thesis
author Ng , Hoong Chin
author_facet Ng , Hoong Chin
author_sort Ng , Hoong Chin
title A Cost And Power Efficient Ddr4/Gddr5x/Gddr5 Transmitter With 3-Tap Equalizer
title_short A Cost And Power Efficient Ddr4/Gddr5x/Gddr5 Transmitter With 3-Tap Equalizer
title_full A Cost And Power Efficient Ddr4/Gddr5x/Gddr5 Transmitter With 3-Tap Equalizer
title_fullStr A Cost And Power Efficient Ddr4/Gddr5x/Gddr5 Transmitter With 3-Tap Equalizer
title_full_unstemmed A Cost And Power Efficient Ddr4/Gddr5x/Gddr5 Transmitter With 3-Tap Equalizer
title_sort cost and power efficient ddr4/gddr5x/gddr5 transmitter with 3-tap equalizer
publishDate 2016
url http://eprints.usm.my/41304/1/NG_HOONG_CHIN_24_Pages.pdf
http://eprints.usm.my/41304/
_version_ 1643710183454539776
score 13.211869

Similar Items