CMOS technology for increasing efficiency of clock gating techniques using tri-state buffer
Clock gating is an effective technique of decreasing dynamic power dissipation in synchronous design. One of the methods used to realize this goal is to mask the clock which goes to the unnecessary to use in specific time. This paper will present a comparative analysis of this clock gating technique...
Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Institute of Research and Development, Walailak University
2017
|
| Online Access: | http://psasir.upm.edu.my/id/eprint/61131/1/CMOS%20technology%20for%20increasing%20efficiency%20of%20clock%20gating%20techniques%20using%20tri-state%20buffer.pdf http://psasir.upm.edu.my/id/eprint/61131/ http://wjst.wu.ac.th |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|