Evaluation of optimum scan chain parameter with respect to its power performance of CORTEXM0DS
Design-for-test (DFT) in an integrated circuit is one of essential parts in System-on-Chip. DFT enables testing and debugging of an integrated circuit before it is being produced in high volume. Due to increasing of functionality in advanced nodes of integrated circuit designs, DFT is imperative in...
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| Main Authors: | , , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2017
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| Online Access: | http://psasir.upm.edu.my/id/eprint/59512/1/Evaluation%20of%20optimum%20scan%20chain%20parameter%20with%20respect%20to%20its%20power%20performance%20of%20CORTEXM0DS.pdf http://psasir.upm.edu.my/id/eprint/59512/ |
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