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Evaluation of optimum scan chain parameter with respect to its power performance of CORTEXM0DS

Design-for-test (DFT) in an integrated circuit is one of essential parts in System-on-Chip. DFT enables testing and debugging of an integrated circuit before it is being produced in high volume. Due to increasing of functionality in advanced nodes of integrated circuit designs, DFT is imperative in...

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Main Authors: Latip, Nur Amirah, Kamsani, Noor Ain, Lee, Yuen Tat, Rokhani, Fakhrul Zaman, Mohd Sidek, Roslina
Format: Conference or Workshop Item
Language:English
Published: IEEE 2017
Online Access:http://psasir.upm.edu.my/id/eprint/59512/1/Evaluation%20of%20optimum%20scan%20chain%20parameter%20with%20respect%20to%20its%20power%20performance%20of%20CORTEXM0DS.pdf
http://psasir.upm.edu.my/id/eprint/59512/
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spelling my.upm.eprints.595122018-03-08T01:03:26Z http://psasir.upm.edu.my/id/eprint/59512/ Evaluation of optimum scan chain parameter with respect to its power performance of CORTEXM0DS Latip, Nur Amirah Kamsani, Noor Ain Lee, Yuen Tat Rokhani, Fakhrul Zaman Mohd Sidek, Roslina Design-for-test (DFT) in an integrated circuit is one of essential parts in System-on-Chip. DFT enables testing and debugging of an integrated circuit before it is being produced in high volume. Due to increasing of functionality in advanced nodes of integrated circuit designs, DFT is imperative in reducing defect counts and improving performance of the integrated circuits before reaching the customers. Thus, many research have been done in DFT area in achieving an optimum performance of integrated circuits. Scan test is one of the DFT techniques that enable the integrated circuit design to be tested and debugged. However, due to additional components are being inserted to improve the controllability and observability, high power consumption and dissipation is expected. In this paper, an evaluation of optimum scan chain parameter with respect to its power performance of an integrated circuit will be performed. A block of a microcontroller unit, CORTEXM0DS will be used to where by the scan cells are inserted using DFT Compiler and TetraMAX ATPG from Synopsys. Scan chain from 2 to 20 chains with increment of 2 is simulated and the test power is obtained. The simulation result shows that scan chain with 16 chains count in the design contributed the highest test power of 15.5409 mW while scan chain with 10 chains count result in the lowest test power of 15.2842 mW. The optimum scan chain will also consider the number of test coverage and test pattern. IEEE 2017 Conference or Workshop Item PeerReviewed text en http://psasir.upm.edu.my/id/eprint/59512/1/Evaluation%20of%20optimum%20scan%20chain%20parameter%20with%20respect%20to%20its%20power%20performance%20of%20CORTEXM0DS.pdf Latip, Nur Amirah and Kamsani, Noor Ain and Lee, Yuen Tat and Rokhani, Fakhrul Zaman and Mohd Sidek, Roslina (2017) Evaluation of optimum scan chain parameter with respect to its power performance of CORTEXM0DS. In: 2017 IEEE 15th Student Conference on Research and Development (SCOReD), 13-14 Dec. 2017, Putrajaya, Malaysia. (pp. 127-130). 10.1109/SCORED.2017.8305408
institution Universiti Putra Malaysia
building UPM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Putra Malaysia
content_source UPM Institutional Repository
url_provider http://psasir.upm.edu.my/
language English
description Design-for-test (DFT) in an integrated circuit is one of essential parts in System-on-Chip. DFT enables testing and debugging of an integrated circuit before it is being produced in high volume. Due to increasing of functionality in advanced nodes of integrated circuit designs, DFT is imperative in reducing defect counts and improving performance of the integrated circuits before reaching the customers. Thus, many research have been done in DFT area in achieving an optimum performance of integrated circuits. Scan test is one of the DFT techniques that enable the integrated circuit design to be tested and debugged. However, due to additional components are being inserted to improve the controllability and observability, high power consumption and dissipation is expected. In this paper, an evaluation of optimum scan chain parameter with respect to its power performance of an integrated circuit will be performed. A block of a microcontroller unit, CORTEXM0DS will be used to where by the scan cells are inserted using DFT Compiler and TetraMAX ATPG from Synopsys. Scan chain from 2 to 20 chains with increment of 2 is simulated and the test power is obtained. The simulation result shows that scan chain with 16 chains count in the design contributed the highest test power of 15.5409 mW while scan chain with 10 chains count result in the lowest test power of 15.2842 mW. The optimum scan chain will also consider the number of test coverage and test pattern.
format Conference or Workshop Item
author Latip, Nur Amirah
Kamsani, Noor Ain
Lee, Yuen Tat
Rokhani, Fakhrul Zaman
Mohd Sidek, Roslina
spellingShingle Latip, Nur Amirah
Kamsani, Noor Ain
Lee, Yuen Tat
Rokhani, Fakhrul Zaman
Mohd Sidek, Roslina
Evaluation of optimum scan chain parameter with respect to its power performance of CORTEXM0DS
author_facet Latip, Nur Amirah
Kamsani, Noor Ain
Lee, Yuen Tat
Rokhani, Fakhrul Zaman
Mohd Sidek, Roslina
author_sort Latip, Nur Amirah
title Evaluation of optimum scan chain parameter with respect to its power performance of CORTEXM0DS
title_short Evaluation of optimum scan chain parameter with respect to its power performance of CORTEXM0DS
title_full Evaluation of optimum scan chain parameter with respect to its power performance of CORTEXM0DS
title_fullStr Evaluation of optimum scan chain parameter with respect to its power performance of CORTEXM0DS
title_full_unstemmed Evaluation of optimum scan chain parameter with respect to its power performance of CORTEXM0DS
title_sort evaluation of optimum scan chain parameter with respect to its power performance of cortexm0ds
publisher IEEE
publishDate 2017
url http://psasir.upm.edu.my/id/eprint/59512/1/Evaluation%20of%20optimum%20scan%20chain%20parameter%20with%20respect%20to%20its%20power%20performance%20of%20CORTEXM0DS.pdf
http://psasir.upm.edu.my/id/eprint/59512/
_version_ 1643837093617598464
score 13.211869

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