A programmable CMOS delay line for wide delay range generation and duty-cycle adjustability
A programmable CMOS delay line circuit with microsecond delay range and adjustable duty cycle is proposed. Through circuit simulation, approximately 2µs delay range can be achieved using 10-bit counter operating at a clock frequency of 500MHz. Utilising synchronous counters instead of synchronous la...
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| 主要な著者: | , , , , |
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| フォーマット: | 論文 |
| 言語: | English |
| 出版事項: |
Universiti Putra Malaysia Press
2017
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| オンライン･アクセス: | http://psasir.upm.edu.my/id/eprint/55852/1/15-JTS%28S%29-0129-2016-4thProof.pdf http://psasir.upm.edu.my/id/eprint/55852/ http://www.pertanika.upm.edu.my/Pertanika%20PAPERS/JST%20Vol.%2025%20(S)%20Feb.%202017/15-JTS(S)-0129-2016-4thProof.pdf |
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