A programmable CMOS delay line for wide delay range generation and duty-cycle adjustability
A programmable CMOS delay line circuit with microsecond delay range and adjustable duty cycle is proposed. Through circuit simulation, approximately 2µs delay range can be achieved using 10-bit counter operating at a clock frequency of 500MHz. Utilising synchronous counters instead of synchronous la...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Universiti Putra Malaysia Press
2017
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| Online Access: | http://psasir.upm.edu.my/id/eprint/55852/1/15-JTS%28S%29-0129-2016-4thProof.pdf http://psasir.upm.edu.my/id/eprint/55852/ http://www.pertanika.upm.edu.my/Pertanika%20PAPERS/JST%20Vol.%2025%20(S)%20Feb.%202017/15-JTS(S)-0129-2016-4thProof.pdf |
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| Summary: | A programmable CMOS delay line circuit with microsecond delay range and adjustable duty cycle is proposed. Through circuit simulation, approximately 2µs delay range can be achieved using 10-bit counter operating at a clock frequency of 500MHz. Utilising synchronous counters instead of synchronous latches has significantly reduced the large occupied active silicon area as well as the huge power consumption. The generated coarse time delay has shown excellent linearity and immunity to PVT variations. The proposed CMOS delay line is designed using a standard 0.13µm Silterra CMOS technology. The active layout area is (101 x 142) µm2, and the total power consumption is only 0.1 µW. |
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