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A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI

Data-retention flip-flops (DR-FFs) efficiently maintain data during sleep mode, and retain state during transitions between active and sleep mode. This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to n...

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Main Authors: Ji, Yuxin, Zhang, Yuhang, Chen, Changyan, Zhao, Jian, Rokhani, Fakhrul Zaman, Ismail, Yehea, Li, Yongfu
Format: Article
Published: Institute of Electrical and Electronics Engineers 2024
Online Access:http://psasir.upm.edu.my/id/eprint/114238/
https://ieeexplore.ieee.org/document/10684787/
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spelling my.upm.eprints.1142382025-01-08T06:21:21Z http://psasir.upm.edu.my/id/eprint/114238/ A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI Ji, Yuxin Zhang, Yuhang Chen, Changyan Zhao, Jian Rokhani, Fakhrul Zaman Ismail, Yehea Li, Yongfu Data-retention flip-flops (DR-FFs) efficiently maintain data during sleep mode, and retain state during transitions between active and sleep mode. This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to near/subthreshold, achieving a sleep mode leakage power of 12.2 pW, 1.4 × -3.8 × less than the prior CMOS DR-FFs. Our proposed DR-FFs consume the lowest active mode switching efficiency of 36.5 fJ/step, 1.2 × -4 × less than the prior works, and a comparable transition efficiency of 1.9 fJ/step. Furthermore, our proposed DR-FFs require minimal control signals, logic gates, and switches, significantly reducing design complexity, and avoiding the drawbacks of nonvolatile data retention FFs (NV-FFs). Institute of Electrical and Electronics Engineers 2024-09-20 Article PeerReviewed Ji, Yuxin and Zhang, Yuhang and Chen, Changyan and Zhao, Jian and Rokhani, Fakhrul Zaman and Ismail, Yehea and Li, Yongfu (2024) A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. pp. 1-5. ISSN 1063-8210; eISSN: 1557-9999 https://ieeexplore.ieee.org/document/10684787/ 10.1109/TVLSI.2024.3453946
institution Universiti Putra Malaysia
building UPM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Putra Malaysia
content_source UPM Institutional Repository
url_provider http://psasir.upm.edu.my/
description Data-retention flip-flops (DR-FFs) efficiently maintain data during sleep mode, and retain state during transitions between active and sleep mode. This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to near/subthreshold, achieving a sleep mode leakage power of 12.2 pW, 1.4 × -3.8 × less than the prior CMOS DR-FFs. Our proposed DR-FFs consume the lowest active mode switching efficiency of 36.5 fJ/step, 1.2 × -4 × less than the prior works, and a comparable transition efficiency of 1.9 fJ/step. Furthermore, our proposed DR-FFs require minimal control signals, logic gates, and switches, significantly reducing design complexity, and avoiding the drawbacks of nonvolatile data retention FFs (NV-FFs).
format Article
author Ji, Yuxin
Zhang, Yuhang
Chen, Changyan
Zhao, Jian
Rokhani, Fakhrul Zaman
Ismail, Yehea
Li, Yongfu
spellingShingle Ji, Yuxin
Zhang, Yuhang
Chen, Changyan
Zhao, Jian
Rokhani, Fakhrul Zaman
Ismail, Yehea
Li, Yongfu
A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI
author_facet Ji, Yuxin
Zhang, Yuhang
Chen, Changyan
Zhao, Jian
Rokhani, Fakhrul Zaman
Ismail, Yehea
Li, Yongfu
author_sort Ji, Yuxin
title A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI
title_short A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI
title_full A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI
title_fullStr A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI
title_full_unstemmed A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI
title_sort 0.4 v, 12.2 pw leakage, 36.5 fj/step switching efficiency data retention flip-flop in 22 nm fdsoi
publisher Institute of Electrical and Electronics Engineers
publishDate 2024
url http://psasir.upm.edu.my/id/eprint/114238/
https://ieeexplore.ieee.org/document/10684787/
_version_ 1821003748593369088
score 13.232389

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