A 0.4 V, 12.2 pW leakage, 36.5 fJ/step switching efficiency data retention flip-flop in 22 nm FDSOI
Data-retention flip-flops (DR-FFs) efficiently maintain data during sleep mode, and retain state during transitions between active and sleep mode. This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to n...
Saved in:
| Main Authors: | , , , , , , |
|---|---|
| Format: | Article |
| Published: |
Institute of Electrical and Electronics Engineers
2024
|
| Online Access: | http://psasir.upm.edu.my/id/eprint/114238/ https://ieeexplore.ieee.org/document/10684787/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | Data-retention flip-flops (DR-FFs) efficiently maintain data during sleep mode, and retain state during transitions between active and sleep mode. This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to near/subthreshold, achieving a sleep mode leakage power of 12.2 pW, 1.4 × -3.8 × less than the prior CMOS DR-FFs. Our proposed DR-FFs consume the lowest active mode switching efficiency of 36.5 fJ/step, 1.2 × -4 × less than the prior works, and a comparable transition efficiency of 1.9 fJ/step. Furthermore, our proposed DR-FFs require minimal control signals, logic gates, and switches, significantly reducing design complexity, and avoiding the drawbacks of nonvolatile data retention FFs (NV-FFs). |
|---|