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Neural Network Based Pattern Recognition in Visual Inspection System for Intergrated Circuit Mark Inspection

Industrial visual machine inspection system uses template or feature matching methods to locate or inspect parts or pattern on parts. These algorithms could not compensate for the change or variation on the inspected parts dynamically. Such problem was faced by a multinational semiconductor manuf...

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Main Author: Sevamalai, Venantius Kumar
Format: Thesis
Language:English
English
Published: 1998
Subjects:
Neural networks (Computer science) - Case studies
Online Access:http://psasir.upm.edu.my/id/eprint/10131/1/FK_1998_8_A.pdf
http://psasir.upm.edu.my/id/eprint/10131/
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spelling my.upm.eprints.101312024-03-15T03:29:46Z http://psasir.upm.edu.my/id/eprint/10131/ Neural Network Based Pattern Recognition in Visual Inspection System for Intergrated Circuit Mark Inspection Sevamalai, Venantius Kumar Industrial visual machine inspection system uses template or feature matching methods to locate or inspect parts or pattern on parts. These algorithms could not compensate for the change or variation on the inspected parts dynamically. Such problem was faced by a multinational semiconductor manufacturer. Therefore a study was conducted to introduce a new algorithm to inspect integrated circuit package markings. The main intend of the system was to verify if the marking can be read by humans. Algorithms that the current process uses however, was not capable in handling mark variations that was introduced by the marking process. A neural network based pattern recognition system was implemented and tested on images resembling the parts variations. Feature extraction was made simple by sectioning the region of interest (ROI) on the image into a specified (by the user) number of sections. The ratio of object pixels to the entire area of each section is calculated and used as an input into a feedforward neural network. Error-back propagation algorithm was used to train the network. The objective was to test the robustness of the network in handling pattern variations as well as the feasibility of implementing it on the production floor in tetms of execution speed. Two separate programme modules were written in C++; one for feature extraction and another for neural networks classifier. The feature extraction module was tested for its speed using various ROI sizes. The time taken for processing was round to be almost linearly related to the ROJ size and not at all effected by the number of sections. The minimum ROJ setting (200 X 200 pixels) was considerably slower at 5 5ms compared to what was required - 20ms. The neural networks c1assifier was very successful in classifying 1 3 different image patterns by learning from 4 training patterns. The classifier also clocked an average speed of 9.6ms which makes it feasible to implement it on the production floor. As a final say, it can be concluded that by carefully surveying the choices of hardware and software and its appropriate combination, this system can be seriously considered for implementation on the semiconductor production floor. 1998-05 Thesis NonPeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/10131/1/FK_1998_8_A.pdf Sevamalai, Venantius Kumar (1998) Neural Network Based Pattern Recognition in Visual Inspection System for Intergrated Circuit Mark Inspection. Masters thesis, Universiti Putra Malaysia. Neural networks (Computer science) - Case studies English
institution Universiti Putra Malaysia
building UPM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Putra Malaysia
content_source UPM Institutional Repository
url_provider http://psasir.upm.edu.my/
language English
English
topic Neural networks (Computer science) - Case studies
spellingShingle Neural networks (Computer science) - Case studies
Sevamalai, Venantius Kumar
Neural Network Based Pattern Recognition in Visual Inspection System for Intergrated Circuit Mark Inspection
description Industrial visual machine inspection system uses template or feature matching methods to locate or inspect parts or pattern on parts. These algorithms could not compensate for the change or variation on the inspected parts dynamically. Such problem was faced by a multinational semiconductor manufacturer. Therefore a study was conducted to introduce a new algorithm to inspect integrated circuit package markings. The main intend of the system was to verify if the marking can be read by humans. Algorithms that the current process uses however, was not capable in handling mark variations that was introduced by the marking process. A neural network based pattern recognition system was implemented and tested on images resembling the parts variations. Feature extraction was made simple by sectioning the region of interest (ROI) on the image into a specified (by the user) number of sections. The ratio of object pixels to the entire area of each section is calculated and used as an input into a feedforward neural network. Error-back propagation algorithm was used to train the network. The objective was to test the robustness of the network in handling pattern variations as well as the feasibility of implementing it on the production floor in tetms of execution speed. Two separate programme modules were written in C++; one for feature extraction and another for neural networks classifier. The feature extraction module was tested for its speed using various ROI sizes. The time taken for processing was round to be almost linearly related to the ROJ size and not at all effected by the number of sections. The minimum ROJ setting (200 X 200 pixels) was considerably slower at 5 5ms compared to what was required - 20ms. The neural networks c1assifier was very successful in classifying 1 3 different image patterns by learning from 4 training patterns. The classifier also clocked an average speed of 9.6ms which makes it feasible to implement it on the production floor. As a final say, it can be concluded that by carefully surveying the choices of hardware and software and its appropriate combination, this system can be seriously considered for implementation on the semiconductor production floor.
format Thesis
author Sevamalai, Venantius Kumar
author_facet Sevamalai, Venantius Kumar
author_sort Sevamalai, Venantius Kumar
title Neural Network Based Pattern Recognition in Visual Inspection System for Intergrated Circuit Mark Inspection
title_short Neural Network Based Pattern Recognition in Visual Inspection System for Intergrated Circuit Mark Inspection
title_full Neural Network Based Pattern Recognition in Visual Inspection System for Intergrated Circuit Mark Inspection
title_fullStr Neural Network Based Pattern Recognition in Visual Inspection System for Intergrated Circuit Mark Inspection
title_full_unstemmed Neural Network Based Pattern Recognition in Visual Inspection System for Intergrated Circuit Mark Inspection
title_sort neural network based pattern recognition in visual inspection system for intergrated circuit mark inspection
publishDate 1998
url http://psasir.upm.edu.my/id/eprint/10131/1/FK_1998_8_A.pdf
http://psasir.upm.edu.my/id/eprint/10131/
_version_ 1794564281885261824
score 13.211869

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