Optimizing 35nm NMOS devices V TH and I LEAK by controlling active area and halo implantation dosage
CMOS transistor reaches physical and electrical limitations technology passes through the critical 90 nm gate size. Scaling down linearly to 35nm, the transistor electrical characteristics behave even more unpredictable. This can be seen with leakage current increasing exponentially as the physical...
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| Main Authors: | , , , , , |
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| Format: | Conference Proceeding |
| Published: |
2017
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| Online Access: | http://dspace.uniten.edu.my:80/jspui/handle/123456789/5237 |
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