Design and optimization of 22nm NMOS transistor
In this paper, we investigate the effects of four process parameters and two process noise parameters on the threshold voltage (V th) of a 22nm NMOS transistor. We used TiO 2 as the high-k material to replace the SiO 2 dielectric. The NMOS transistor was simulated using the fabrication tool ATHENA a...
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| Main Authors: | , , , , , , |
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| Format: | |
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2017
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| Online Access: | http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5228 |
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