Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method
This paper describes our investigation of the effect of seven processes' parameters on threshold voltage (VTH) in the fabrication of a 32nm CMOS transistor. The parameters are HALO implantation, S/D Implantation, Compensation implantations, SiO2 thickness, VTH adjustment implantation, polysilic...
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2017
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| Online Access: | http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5222 |
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| Summary: | This paper describes our investigation of the effect of seven processes' parameters on threshold voltage (VTH) in the fabrication of a 32nm CMOS transistor. The parameters are HALO implantation, S/D Implantation, Compensation implantations, SiO2 thickness, VTH adjustment implantation, polysilicon thickness and silicide annealing time. The setting of process parameters were determined by Taguchi method L18 experimental design. From there, the level of importance of each of the process parameters on threshold voltage was determined using analysis of variance (ANOVA). Transistor fabrication was performed by using Silvaco ATHENA module. Silvaco ATLAS module takes care of electrical characterization for the device. These two simulators results were analyzed with Taguchi method to aid in design and optimizing process parameters. Threshold voltage (VTH) results were used as the evaluation parameters. The results show that the VTH value 0.1099 V for NMOS can be achieved respectively, much closer to the ITRS prediction than our previous L9 experiment result. As the conclusion, by utilizing L18 Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.1099 V that is well within ITRS 2003 prediction for 32nm transistor © 2012 American Institute of Physics. |
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